Metal Gate Height Compensation Through Dielectric Polishing
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Solution Overview
Problem
The Metal Gate process introduces significant height differences between large-size and small-size gates due to chemical-mechanical polishing, leading to performance bottlenecks, with existing solutions either reducing polishing time or making large-size gates taller, which are inefficient.
Innovation Solution
A method involving forming dummy gate structures on a silicon substrate, depositing an interlayer dielectric layer, and controlling its polishing to create trenches where an aluminum layer is deposited and polished, ensuring the height difference between large-size and small-size metal gates is minimized by adjusting the polishing of the interlayer dielectric and aluminum layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing is applied to metal gates, then the metal gate surface is planarized, but the height difference between large-size and small-size gates increases to more than 200 Å
Solution Approach 1:
The patent applies preliminary action by performing interlayer dielectric polishing before metal gate formation to pre-establish a height compensation of approximately 100 Å between large-size and small-size gate regions. This preliminary height adjustment counteracts the subsequent metal gate polishing effect, reducing the final height difference from over 200 Å to approximately 100 Å or less
Solution Approach 2:
The patent changes the parameter of interlayer dielectric layer thickness in different regions to compensate for expected metal gate height differences. By making the interlayer dielectric layer thicker in large-size gate regions and thinner in small-size gate regions, the patent pre-compensates for the differential polishing that will occur during metal gate processing
2Manufacturing precision
If large-size gates are made taller in advance, then height loss from polishing is compensated, but process complexity increases
Solution Approach 1:
The patent uses the interlayer dielectric layer formation process to serve multiple functions: it provides electrical isolation and simultaneously establishes the height compensation profile needed for subsequent metal gate polishing. This multi-functionality avoids adding separate complexity-increasing steps while achieving gate height compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the height difference between large-size and small-size metal gates, preventing pit formation and shortening polishing time, thereby improving device performance by maintaining consistent gate heights during the polishing process.
Implementation Method 1
the necessary metal gate chemical-mechanical polishing has been added
Implementation Method 2
polishing speed of large-size gate area is faster than that of small-size gate area
Implementation Method 3
depositing an interlayer dielectric layer on the silicon nitride layer
Data Source
AI summary
A method for improving a height difference between gates comprises steps of: forming small-size and large-size dummy gate structures on a substrate; forming a silicon nitride layer on the gates; depositing an interlayer dielectric layer on the silicon nitride layer; polishing the interlayer dielectric layer until the top surfaces of the large-size dummy gate structures are approximately 110 Å more than the top surface of the small-size dummy gate structures; removing the small-size and large-size dummy gate structures to form trenches, the height of the silicon nitride layer on sidewalls of the trenches is the same as the height of the adjacent interlayer dielectric layer; depositing an aluminum layer to fill the trenches and cover the dielectric material on the top surface of interlayer dielectric layer.