Metal Gate Height Control Using a Sacrificial Epitaxial Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional manufacturing processes for integrated circuit (IC) devices struggle with highly variable etching or polishing steps that result in excessive gate heights, leading to increased gate capacitances and reduced operating frequencies, which are exacerbated by the pressure to shrink transistor densities and critical dimensions.
Innovation Solution
A method is introduced that uses a sacrificial layer over a channel material in a material stack, deposited through epitaxy to achieve a well-controlled thickness, allowing for precise control of metal gate height, and is combined with a hardmask layer for etch selectivity and protection, enabling uniform processing and consistent gate spacer composition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching or polishing steps are used to set gate heights, then manufacturing process simplicity is maintained, but gate height variations increase and gate heights become excessive
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer with a predetermined thickness before the main gate formation process. This sacrificial layer serves as a pre-established reference that defines the final gate height, allowing subsequent etching or polishing to stop at the correct depth. The thickness of the sacrificial layer is carefully controlled during deposition to ensure the desired gate height is achieved after removal of the sacrificial material.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the substrate and the gate structure. It provides a temporary structural reference that mediates the height control process, enabling precise gate height definition without requiring direct measurement or complex control during the gate formation itself. After serving its purpose, the sacrificial layer is removed, leaving the precisely controlled gate structure.
2Reliability
If gate heights are reduced to improve operating frequency, then parasitic capacitances decrease, but gate height control precision becomes more critical
Solution Approach 1:
By pre-forming the sacrificial layer with precisely controlled thickness, the patent establishes the gate height reference before any variable processing steps. This preliminary action ensures that even when gate heights are reduced to improve operating frequency, the control precision is maintained because the target height is defined by the sacrificial layer thickness rather than by subsequent variable etching or polishing parameters.
Solution Approach 2:
The patent changes the control parameter from post-deposition measurement and adjustment to pre-deposition thickness control of the sacrificial layer. By controlling the deposition parameters (temperature, pressure, gas flow, deposition rate) to achieve precise sacrificial layer thickness, the gate height control precision is improved, enabling reduced gate heights that lower parasitic capacitances and improve operating frequency.
3Productivity
If transistor densities are increased by shrinking critical dimensions, then device integration is improved, but gate height variations have greater significance
Solution Approach 1:
The sacrificial layer provides a pre-established height reference that remains consistent across multiple transistors, ensuring uniform gate height control even as critical dimensions are shrunk to increase transistor density. This preliminary reference structure prevents gate height variations from becoming more significant at smaller scales.
Solution Approach 2:
The patent changes from controlling gate height through variable post-processing to controlling it through pre-defined sacrificial layer thickness. This parameter change ensures that gate height variation is minimized even when transistor densities are increased by shrinking critical dimensions, because the height control is decoupled from the dimensional scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate height variations, facilitates scaling down of IC devices, and improves performance by minimizing parasitic capacitances, resulting in higher operating frequencies and more uniform processing.
Implementation Method 1
deposited through epitaxy to achieve a well-controlled thickness
Data Source
AI summary
Integrated circuit (IC) devices with non-planar transistors may be formed from a material stack having a sacrificial layer between one or more mask material layers and a top surface of a channel material. An IC device may include a non-planar transistor with a gate spacer layer having portions with a same or consistent composition, both over an upper surface of the channel material and under a lower surface of the channel material. The gate spacer layer may have a different composition than a gate endcap spacer layer.