3 nm Metal Gate Height Layout for CMP Reliability
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, manufacturing becomes more challenging due to issues like over-polishing during chemical-mechanical planarization (CMP) processes, which affect device performance and reliability.
Innovation Solution
A method for manufacturing semiconductor devices with improved topography by distributing devices of various gate heights across a semiconductor die, which helps in achieving better integrated circuit performance and manufacturing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate height is reduced to improve circuit performance, then capacitance decreases and performance improves, but manufacturing reliability deteriorates due to over-polishing during CMP processes
Solution Approach 1:
The patent applies local quality by distributing different gate heights across different regions of the semiconductor die. Specifically, first devices are formed with a first gate height in a first region, while second devices are formed with a second gate height in a second region. This spatial variation in gate height allows optimization of device performance in certain regions while maintaining manufacturing reliability in others, thereby resolving the contradiction between performance improvement and manufacturing reliability.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision deteriorates due to over-polishing issues
Solution Approach 1:
The patent implements local quality by creating regions with different gate heights across the semiconductor die. This allows the manufacturing process to accommodate variations at reduced minimum feature sizes by having some regions with larger gate heights that are less susceptible to over-polishing, thereby maintaining manufacturing precision while achieving high integration density through overall miniaturization.
Data Source
AI summary
Provided are semiconductor dies and methods for manufacturing semiconductor devices on a die. A method for manufacturing semiconductor devices on a die includes forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm).