Metal Gate Height Preservation via Polysilicon Protecting Layer
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Solution Overview
Problem
Conventional metal gate manufacturing methods, particularly the gate last process, face challenges with height loss and reliability issues due to the consumption of polysilicon layers during chemical mechanical polishing, leading to reduced gate height and adverse electrical performance.
Innovation Solution
A manufacturing method that involves forming a protecting layer on the polysilicon layer to prevent consumption during CMP processes, ensuring the dummy gate's original height is maintained, and subsequently forming a metal gate with the same height in the gate trench, using a multilayered dielectric structure and etching processes to preserve the polysilicon layer's height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate last process is used to provide more material choices, then material versatility is improved, but height loss occurs due to polysilicon consumption
Solution Approach 1:
The protecting layer is formed in advance on the polysilicon layer before any subsequent processing steps. This preliminary protection ensures that regardless of which materials are chosen for the high-k gate dielectric layer or metal gate, the polysilicon layer's height is preserved, maintaining gate height accuracy while allowing full material versatility.
Solution Approach 2:
The protecting layer is a sacrificial, temporary structure that is intentionally designed to be consumed or removed after serving its protective function. It is a cost-effective solution that protects the valuable polysilicon layer during processing, then can be removed or left as part of the final structure without impacting the gate height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures the metal gate retains the original height of the dummy gate, enhancing its electrical performance and reliability by preventing height loss and material consumption, thus addressing the integration challenges of the gate last process.
Implementation Method 1
a planarization process, such as a chemical mechanical polishing (CMP) process is performed to remove a portion of the ILD layer 116 and the CESL 114
Implementation Method 2
performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate
Data Source
AI summary
A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.