Metal Gate Integration Without Sidewall Spacers

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Solution Overview

Problem

Polysilicon gates in semiconductor devices have limitations due to depletion of charge carriers at the gate dielectric interface, leading to inefficiencies, prompting the need for alternative gate materials like metal gates, but existing metal gate manufacturing processes face challenges such as defects from sidewall spacer removal and recessed areas during replacement gate integration.

Innovation Solution

The process involves forming sacrificial gates, source/drain extensions, and sidewall spacers, followed by removing the spacers and depositing a nitride layer, which allows for the removal of the sacrificial gate and formation of metal gates between the nitride portions, eliminating sidewall spacers and reducing defects by avoiding recessed areas during metal deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional replacement gate integration scheme with sidewall spacers is used, then metal gate formation is achieved, but defects and recessed areas are created during sidewall spacer removal

Engineering Contradiction:
Improvedevice yieldVSAvoidsidewall spacer defects
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent removes sidewall spacers from the manufacturing process entirely. Instead of forming sidewall spacers and then removing them (which creates defects), the process directly forms metal gates adjacent to sacrificial gates without using sidewall spacers as intermediaries. This extraction of the problematic component eliminates the source of defects and recessed areas.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary actions by forming the metal gate material and patterning it before sacrificial gate removal. The metal gate is formed in a first pre-metal dielectric layer, then the sacrificial gate is removed, leaving the metal gate properly positioned. This preliminary formation avoids the need for subsequent complex steps involving sidewall spacer removal that would create defects.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If sidewall spacers are used during replacement gate integration, then source/drain offset is achieved, but manufacturing complexity and defect density increase

Engineering Contradiction:
Improvesource/drain alignmentVSAvoidprocess steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the sidewall spacer component from the process. Source/drain offset is achieved through alternative means such as direct patterning or self-alignment techniques during metal gate formation, removing the need for sidewall spacers and their subsequent removal, thereby simplifying the manufacturing process.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The metal gate formation process serves multiple functions: it provides the gate electrode, establishes source/drain offset, and creates the necessary structural boundaries. By making the metal gate formation multi-functional, the process eliminates the need for separate sidewall spacer steps, reducing overall process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If polysilicon gates are doped to adjust work function, then gate charge carrier supply is limited, but manufacturing flexibility is maintained

Engineering Contradiction:
Improvework function adjustmentVSAvoidcharge carrier supply
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent changes the fundamental parameter of gate material from polysilicon to metal. Metals provide inherently higher charge carrier density without requiring heavy doping. The work function of metal gates can still be adjusted by selecting different metal materials or metal combinations, maintaining adaptability while dramatically increasing charge carrier supply.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite metal gate structures, such as metal layers combined with metal nitride layers or other metal combinations. These composite structures allow tuning of work function while maintaining high charge carrier density, achieving both adaptability and superior electrical performance compared to doped polysilicon.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces defects and enhances manufacturability by eliminating sidewall spacer-related issues, improving yield and performance by allowing for uniform metal gate formation without the need for conventional sidewall spacers, thus improving the reliability and efficiency of semiconductor devices.

Implementation Method 1

depositing a nitride layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing a nitride layer

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

The sacrificial gate located between the portions of the nitride layer is removed

Methodology Applied
Scientific EffectPlasma Etching: Plasma

Data Source

PatentUS7795097B2Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme
Publication Date: 2010.09.14 TEXAS INSTRUMENTS INC
  • US7795097B2 patent drawing
  • US7795097B2 patent drawing
  • US7795097B2 patent drawing

AI summary

One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.