Silicon-Doped Metal Gate Interface Tuning for Multi-Gate CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the electronics industry is to provide proper threshold voltages for CMOS devices, particularly for multi-gate devices like FinFET and GAA devices, while reducing power consumption, as traditional methods using thick work function metals are ineffective due to the small size of these devices.
Innovation Solution
A method involving a thin work function metal layer doped with silicon, where a silicide layer is deposited over the work function metal layer and annealed to dope silicon into the interface with the high-k gate dielectric layer, creating dipole effects that reduce the effective work function, allowing for efficient tuning of threshold voltages without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If thick work function metals are used for threshold voltage tuning, then traditional planar devices can achieve proper threshold voltages, but multi-gate devices cannot achieve effective threshold voltage tuning due to their small size
Solution Approach 1:
The patent applies local quality by creating a silicon-doped region specifically at the interface between the work function metal layer and the high-k gate dielectric layer. This localized doping at the critical interface region enables effective threshold voltage tuning in multi-gate devices without requiring thick metal layers throughout the entire structure, thus adapting the traditional approach to modern device geometries.
Solution Approach 2:
The patent changes the doping parameter from conventional bulk metal doping to interface-specific silicon doping. By forming a silicide layer and annealing it to drive silicon atoms into the work function metal/high-k dielectric interface, the effective work function is modified through dipole formation, enabling threshold voltage tuning in scaled multi-gate devices where thick metals are not feasible.
2Length of moving object
If the work function metal layer is made thin to accommodate small multi-gate devices, then device scaling is enabled, but threshold voltage tuning becomes ineffective
Solution Approach 1:
The patent concentrates the doping effect locally at the interface between the thin work function metal layer and the high-k gate dielectric. By forming silicon dopant clusters or dipoles specifically at this interface through silicide annealing, the thin metal layer achieves effective threshold voltage tuning without requiring increased thickness, thus maintaining device scaling while restoring tuning capability.
Solution Approach 2:
The patent creates a composite structure at the gate stack interface by forming silicon-doped regions within the work function metal layer adjacent to the high-k dielectric. This composite interface structure, consisting of the thin metal layer combined with silicon dopant clusters, produces dipole effects that enable effective work function modulation despite the reduced metal thickness.
3Ease of manufacture
If conventional doping methods are used in thin work function metal layers, then manufacturing processes remain simple, but effective work function reduction cannot be achieved
Solution Approach 1:
The patent employs preliminary action by first depositing a silicide layer over the work function metal layer before the final metal gate formation. This silicide layer serves as a precursor that, when annealed, drives silicon atoms into the work function metal/high-k dielectric interface to create the desired doping profile and dipole structure, achieving precise work function control through a sequential process approach.
Solution Approach 2:
The silicide layer acts as an intermediary material that facilitates silicon doping of the work function metal layer. By annealing the silicide layer, silicon atoms are released and driven into the interface region, mediating the transfer of dopant atoms from the silicide precursor to the work function metal/high-k dielectric interface, thus achieving precise doping control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the effective work function by approximately 55 mV per 1% silicon dopant concentration, enabling threshold voltage tuning for both NFET and PFET devices, even with very thin work function metal layers, and is applicable to small-sized multi-gate CMOS devices, enhancing performance and reducing power consumption.
Implementation Method 1
annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer
Data Source
AI summary
A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.