Replacement Metal Gate Layout to Limit Isolation Layer Encroachment
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Solution Overview
Problem
Conventional etching techniques for replacing sacrificial gates in semiconductor devices result in excessive rounding or punch etching into the isolation insulating layer, leading to increased parasitic capacitance and reduced electrical conductivity, particularly in sub 20-25 nm technology nodes.
Innovation Solution
A method is employed to minimize the extension of the metal gate into the isolation insulating region near the source/drain region by limiting the etching process, using selective etching and epitaxial layer formation to reduce parasitic capacitance and enhance electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used to replace sacrificial gates with metal gates, then the metal gate can be formed, but the metal gate extends near the source/drain region causing increased parasitic capacitance and reduced electrical conductivity
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with precisely controlled dimensions before metal gate deposition. The mandrel is formed with a specific width that is smaller than the final metal gate width, and is positioned at a controlled distance from the source/drain regions. This preliminary structure guides the subsequent metal gate formation to ensure the metal gate does not extend too close to the source/drain regions, thereby preventing excessive parasitic capacitance while maintaining manufacturing precision.
Solution Approach 2:
The patent uses the mandrel structure as an intermediary element during the metal gate formation process. The mandrel serves as a temporary placeholder that defines the spatial boundaries for the metal gate. By using this intermediary structure, the process achieves precise control over metal gate positioning and dimensions without requiring direct complex patterning of the metal gate itself, thus resolving the contradiction between manufacturing precision and parasitic capacitance control.
2Ease of manufacture
If conventional etching techniques are used to remove sacrificial gates, then the sacrificial gate can be removed, but excessive rounding or punch etching into the isolation insulating layer occurs
Solution Approach 1:
The patent extracts the sacrificial gate removal step from the conventional process and replaces it with a mandrel-based approach. Instead of directly etching away the sacrificial gate material, the process forms a new mandrel structure that serves the same functional purpose. This extraction eliminates the harmful punch etching effect on the isolation insulating layer while maintaining the ease of manufacturing benefits, as the mandrel can be formed using standard deposition and patterning techniques without requiring aggressive etching processes.
3Productivity
If the metal gate is allowed to extend into the isolation insulating region, then manufacturing is simpler, but parasitic capacitance increases and electrical conductivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-defining the optimal metal gate position and dimensions through the mandrel structure formation. The mandrel is created with precise dimensions and positioning that account for the desired electrical performance, eliminating the need for complex post-processing or trial-and-error adjustments. This preliminary structuring maintains manufacturing simplicity while ensuring the metal gate does not extend into regions that would compromise electrical conductivity, thus resolving the contradiction between productivity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces parasitic capacitance, increases electric current, and improves device yield by minimizing the metal gate's extension into the isolation insulating region, thereby optimizing the semiconductor device's performance.
Implementation Method 1
A method is employed to minimize the extension of the metal gate into the isolation insulating region near the source/drain region by limiting the etching process, using selective etching and epitaxial layer formation
Implementation Method 2
A method is employed to minimize the extension of the metal gate into the isolation insulating region near the source/drain region by limiting the etching process, using selective etching and epitaxial layer formation to reduce parasitic capacitance and enhance electrical conductivity
Data Source
AI summary
A method of fabricating a semiconductor device includes forming an isolation insulating layer over a substrate. A sacrificial gate layer is formed over the isolation insulating layer. The sacrificial gate layer is patterned to form sacrificial gate structures. A spacer layer is formed over the sacrificial gate structures. An interlayer dielectric layer is formed over the sacrificial gate structures. The sacrificial gate structures are removed to form openings over the isolation insulating layer. A residual amount of each sacrificial gate structure remains at the bottom of a respective opening over the isolation insulating layer. Metal gate electrodes are formed in the openings. The metal gate electrodes include a first material and the residual amount comprises a second material different from the first material.