Metal Gate Isolation Plug for MOS Poly Depletion
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes suffer from carrier depletion effects, known as poly depletion, which increase the effective gate dielectric thickness and make it difficult to create an inversion layer at the semiconductor surface, necessitating the development of alternative gate structures.
Innovation Solution
The formation of metal gate electrodes or metal silicide gate electrodes, where a long dummy gate is etched, filled with dielectric material, and then replaced with metal gates, allowing for band-edge work functions in NMOS and PMOS devices, and the use of a gate isolation plug to separate and thin the dielectric layers, reducing the gate isolation plug size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate electrodes are used, then the gate structure is simple and easy to manufacture, but carrier depletion effect occurs which increases effective gate dielectric thickness and makes inversion layer creation difficult
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, titanium nitride, or other metal silicides). This material substitution fundamentally alters the electrical properties, eliminating the carrier depletion effect that plagues polysilicon gates. The metal gate provides high carrier density without depletion, enabling effective inversion layer formation while maintaining manufacturability through established metal deposition techniques like CVD, PVD, or ALD.
Solution Approach 2:
The patent employs composite gate structures combining multiple materials to achieve optimal performance. Typical implementations include metal silicide layers (such as tungsten silicide or titanium silicide) combined with metal nitride layers (such as titanium nitride or tantalum nitride). These composite structures provide both the high carrier density of metals and the work function tunability needed for different device types (NMOS and PMOS), while eliminating polysilicon depletion effects.
2Reliability
If metal gate electrodes are formed by etching long dummy gates and filling with dielectric material, then band-edge work functions can be achieved for NMOS and PMOS devices, but the gate isolation plug size increases and process complexity increases
Solution Approach 1:
The patent applies local quality by creating different gate structures in different regions of the device. Separate gate isolation plugs are formed for NMOS and PMOS devices, each optimized for its specific work function requirements. The dummy gate etching and dielectric filling processes are performed locally in regions where metal gates are needed, allowing band-edge work function achievement without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent segments the gate formation process into distinct steps: forming separate dummy gates for different device types, selectively etching these dummy gates, filling with appropriate dielectric materials, and replacing with metal gates having specific work functions. This segmentation allows independent optimization of NMOS and PMOS gate characteristics while managing process complexity through modular fabrication steps.
3Area of stationary object
If gate isolation plug size is reduced, then device area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the gate isolation plugs at an early stage in the fabrication process, before final device assembly. The dummy gates are formed and positioned first, then the isolation plugs are formed around them with controlled dimensions. This preliminary positioning provides reference structures that guide subsequent processing steps, ensuring that even reduced-size isolation plugs are manufactured with adequate precision through cumulative process control rather than relying on single-step precision.
Data Source
AI summary
A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.