Metal Gate Stack Structure for Lower Gate Leakage
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Solution Overview
Problem
As technology nodes shrink, integrated circuit designs face challenges in maintaining device performance due to increased gate leakage, which existing solutions like replacing polysilicon gate electrodes with metal gates and using high-k gate insulator layers do not fully address, particularly in reducing gate leakage and maintaining effective thickness with decreased gate lengths.
Innovation Solution
A method for fabricating a gate structure involves forming a dummy gate stack on a semiconductor substrate, patterning it, removing the dummy gate to create recesses, depositing work function metal layers, and filling these recesses with metal to form a metal gate stack, which includes multiple work function metal layers and a filling metal, optimized for reduced gate leakage and effective thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate oxide thickness is reduced to maintain performance with decreased gate length, then device performance is improved, but gate leakage increases
Solution Approach 1:
The patent employs a composite gate structure consisting of a high-k dielectric layer (such as hafnium oxide, silicon oxide, or silicon oxynitride) combined with a metal gate electrode. This composite structure enables the gate insulator to achieve both thin physical thickness for high performance and high dielectric constant for low leakage, resolving the contradiction between reduced thickness and increased leakage.
2Speed
If polysilicon gate electrode is replaced with metal gate electrode, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent implements a 'gate last' process where the metal gate stack is fabricated as one of the final steps in the manufacturing sequence. This preliminary action approach allows all preceding processes to be completed with standard polysilicon gates, and the metal gate is then formed by depositing metal layers and patterning them to replace the dummy gate, thereby managing process complexity while achieving performance improvement.
3Object-generated harmful factors
If high-k gate insulator layers are used to reduce gate leakage, then gate leakage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes materials with high dielectric constants (k > 3.9) such as hafnium oxide, silicon oxide, and silicon oxynitride for the gate insulator layer. By changing the material parameter (dielectric constant) rather than relying solely on thickness reduction, the patent achieves both low gate leakage and relaxed manufacturing precision requirements for thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate leakage and maintains performance by optimizing the gate structure with multiple work function metal layers and a filling metal, enhancing the semiconductor device's efficiency and reliability.
Implementation Method 1
high dielectric constant (high-k or HK) gate insulator layers are also used which allows to maintain the same effective thickness as would be provided by a typical gate oxide
Implementation Method 2
depositing work function metal layers
Data Source
AI summary
A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.