Metal Gate Capping Layer for Long-Path Resistance Reduction
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Solution Overview
Problem
As semiconductor devices scale down, gate resistance increases, particularly for devices far from the gate via, leading to slower device speed due to longer signal paths and increased time constants.
Innovation Solution
Implementing a low-resistance capping layer over the gate electrode, such as a tungsten-containing layer, to reduce gate resistance by facilitating horizontal signal propagation through a more conductive path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is scaled down to increase functional density, then production efficiency and cost are improved, but gate resistance increases and device speed decreases
Solution Approach 1:
The patent applies local quality by creating a multi-layer gate electrode structure where different material layers are strategically positioned to address specific local needs. The first conductive layer (e.g., tungsten) provides low resistance at the gate via region, while the second conductive layer (e.g., copper) provides low resistance at the gate electrode region, effectively resolving the gate resistance issue at different locations without requiring overall device scaling reversal
Solution Approach 2:
The patent employs composite materials by combining different conductive materials in a layered gate electrode structure. The first conductive layer uses materials with excellent via fill properties (such as tungsten), while the second conductive layer uses materials with superior conductivity (such as copper), creating a composite structure that leverages the strengths of each material to simultaneously reduce gate resistance and maintain device scaling benefits
2Ease of manufacture
If gate via distance to device increases to accommodate layout, then manufacturing is simplified, but gate resistance increases due to longer signal path
Solution Approach 1:
The patent addresses signal integrity over long gate paths by implementing local quality enhancements through a multi-layer conductive structure. The first conductive layer provides stable via connection, while the second conductive layer provides low-resistance signal propagation path across the extended gate electrode region, ensuring reliable signal delivery even when gate via distance is increased for manufacturing convenience
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces gate resistance and improves device performance by minimizing signal loss, especially for devices far from the gate via, resulting in faster operation.
Implementation Method 1
Implementing a low-resistance capping layer over the gate electrode, such as a tungsten-containing layer, to reduce gate resistance by facilitating horizontal signal propagation through a more conductive path
Data Source
AI summary
A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.