Metal Gate Structure With Low-k Spacers for Parasitic Capacitance
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Solution Overview
Problem
As semiconductor technology advances to smaller geometries, parasitic capacitance between the metal gate structure and source/drain contact becomes increasingly problematic, affecting device switching speed, power consumption, and coupling noise, particularly due to the high dielectric constant of gate dielectric layers in multi-layer insulating materials.
Innovation Solution
Implementing a multi-gate device structure, such as a gate-all-around (GAA) transistor, with low-k dielectric materials in gate spacers and interlayer dielectric layers, and employing a combination of low-k and high-k dielectric materials in the gate dielectric layer to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are used in the gate dielectric layer, then gate control is improved, but parasitic capacitance increases
Solution Approach 1:
The gate dielectric layer is segmented into multiple dielectric layers with different dielectric constants. A first dielectric layer with a first dielectric constant is formed adjacent to the semiconductor channel, and a second dielectric layer with a second dielectric constant is formed adjacent to the metal gate electrode, where the second dielectric constant is lower than the first. This segmentation allows the structure to benefit from high-k materials near the channel while reducing parasitic capacitance near the gate electrode.
Solution Approach 2:
Different regions of the gate dielectric layer are assigned different dielectric properties based on their functional requirements. The region adjacent to the semiconductor channel uses a higher dielectric constant material to maximize gate control, while the region adjacent to the metal gate electrode uses a lower dielectric constant material to minimize parasitic capacitance. This local differentiation of material properties resolves the contradiction between gate control and parasitic capacitance.
2Productivity
If transistor dimensions are scaled down to sub-10 nm, then production efficiency is improved, but parasitic capacitance becomes more significant
Solution Approach 1:
The dielectric constant parameter is changed across different layers of the gate dielectric structure. By transitioning from higher dielectric constant materials near the channel to lower dielectric constant materials near the gate electrode, the structure maintains effective gate control at sub-10 nm dimensions while reducing the parasitic capacitance that becomes increasingly significant at smaller scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers parasitic capacitance, enhancing device switching speed, reducing power consumption, and mitigating coupling noise, while maintaining gate control and scalability.
Implementation Method 1
Certain low-k materials having a dielectric constant less than about 5.0, such as a dielectric constant lower than that of silicon oxide (about 3.9), have been suggested as insulator materials for various dielectric layers outside of a gate structure
Data Source
AI summary
A semiconductor device includes a fin-shaped base protruding from a substrate, an isolation feature disposed on sidewalls of the fin-shaped base, nanostructures vertically stacked over the fin-shaped base, and a gate structure. The gate structure includes a gate dielectric layer wrapping around the nanostructures, a first gate electrode disposed on the gate dielectric layer, a second gate electrode disposed on the first gate electrode, and a dielectric spacer disposed on a sidewall of the second gate electrode. The semiconductor device further includes a gate spacer extending along a sidewall of the gate structure. A dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer, and the dielectric constant of the gate dielectric layer is greater than a dielectric constant of the dielectric spacer.