Metal Gate Transistor Stack for Lower EOT and Fewer Interface Defects
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes suffer from carrier depletion effects, known as poly depletion, which increase the effective gate dielectric thickness and hinder the formation of an inversion layer, making it difficult to create transistors with optimal performance.
Innovation Solution
The formation of metal gate electrodes with multiple layers, including a high-k dielectric layer and a metal layer that undergoes annealing to reduce the interfacial layer thickness and increase channel mobility, is used to address the poly depletion issue, resulting in improved transistor performance by reducing the Effective Oxide Thickness (EOT) and enhancing channel mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrodes are used, then the work function can be adjusted to the band-edge of silicon, but carrier depletion effect occurs which increases the effective gate dielectric thickness and hinders inversion layer formation
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or titanium nitride), fundamentally altering the electrical properties to eliminate carrier depletion effects while maintaining adjustable work function through material selection
Solution Approach 2:
The patent employs composite gate structures combining multiple materials (e.g., metal gate with high-k dielectric, or stacked metal layers with different work functions) to achieve both the elimination of poly depletion and the ability to tune work function for n-type and p-type transistors
2Reliability
If metal gate electrodes are formed with multiple layers, then the poly depletion problem is solved and band-edge work functions are achieved, but the formation process becomes more complex involving multiple deposition and CMP steps
Solution Approach 1:
The gate electrode is divided into multiple functional layers (e.g., barrier layer, work function layer, capping layer), where each layer serves a specific purpose: preventing diffusion, adjusting work function, and protecting the structure, respectively. This segmentation allows independent optimization of each layer's properties
Solution Approach 2:
The metal gate structure is designed to perform multiple functions simultaneously: it serves as the electrical gate electrode, provides work function adjustment for different transistor types, acts as a diffusion barrier, and enables stress engineering for mobility enhancement, reducing the need for separate specialized layers
3Productivity
If the interfacial layer thickness is reduced through annealing, then the Effective Oxide Thickness (EOT) is reduced and channel mobility is enhanced, but interface defects and traps may increase
Solution Approach 1:
The patent carefully controls annealing parameters (temperature, time, atmosphere) to achieve the optimal balance: sufficient annealing to reduce interfacial layer thickness and enhance mobility, but not so excessive as to create harmful defects. Post-annealing treatments such as nitrogen or hydrogen exposure are used to passivate any interface traps formed
Solution Approach 2:
An intermediate layer or capping layer is introduced between the metal gate and the semiconductor channel to mediate the interaction: it allows the metal to provide the desired work function and stress effects while protecting the interface from metal diffusion and reducing defect formation during processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces defects and interface traps, improves channel mobility, and stabilizes the high-k dielectric film, leading to enhanced transistor performance and reliability.
Implementation Method 1
a metal layer that undergoes annealing to reduce the interfacial layer thickness and increase channel mobility
Data Source
AI summary
A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.