Metal Gate Dielectric Stack for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor technology advances to smaller geometries, parasitic capacitance between the gate structure and source/drain contact in transistors increases, hindering device switching speed, power consumption, and noise reduction, despite the use of low-k materials and high-k gate dielectric layers.
Innovation Solution
A method involving the formation of a multi-layer dielectric structure with a low-k spacer layer replacing a portion of the high-k dielectric layer, reducing parasitic capacitance by altering the dielectric constant and spacing between the gate and source/drain contacts, integrated into existing semiconductor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric layer is used in gate structure, then electrostatic control and leakage suppression are improved, but parasitic capacitance between gate and source/drain contact increases
Solution Approach 1:
The gate structure is segmented into multiple functional layers: the high-k dielectric layer (maintaining electrostatic control) and the low-k spacer layer (reducing parasitic capacitance). This segmentation allows each layer to perform its specific function independently, resolving the contradiction between maintaining reliability and reducing harmful parasitic effects.
Solution Approach 2:
Different regions of the gate structure are assigned different dielectric properties: the high-k dielectric material is positioned where electrostatic control is needed (adjacent to channel), while the low-k dielectric material is positioned where parasitic capacitance reduction is needed (between gate and source/drain contact). This local differentiation of material properties resolves the contradiction.
2Productivity
If transistor geometry is scaled down to smaller dimensions, then production efficiency and cost are improved, but parasitic capacitance increases due to reduced distance between gate and source/drain contact
Solution Approach 1:
The dielectric constant parameter is changed in the spacer region by introducing low-k dielectric material. This parameter change directly addresses the parasitic capacitance issue that arises from geometric scaling, allowing continued miniaturization without being constrained by increasing parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by up to 30-40%, enhancing switching speed and reducing power consumption while maintaining effective electrostatic control and leakage suppression.
Implementation Method 1
a low-k dielectric layer disposed on the recessed high-k dielectric layer and over the exposed top portion of the sidewalls of the gate spacers. The low-k dielectric layer is laterally stacked between the source/drain contact and the second gate electrode.
Data Source
AI summary
A method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dummy gate structure across the fin structure, depositing gate spacers over sidewalls of the dummy gate structure, removing the dummy gate structure to form a recess, removing the first semiconductor layers, depositing an interfacial layer wrapping the second semiconductor layers, depositing a high-k dielectric layer over the interfacial layer and over the sidewalls of the gate spacers, depositing a first gate electrode over the high-k dielectric layer, recessing the first gate electrode and the high-k dielectric layer to expose a top portion of the sidewalls of the gate spacers, depositing a low-k dielectric layer over the recessed high-k dielectric layer, and depositing a second gate electrode over the first gate electrode.