Metal Gate Contact Plug Formation With Low-k Spacers
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Solution Overview
Problem
The existing methods for forming contact plugs and metal gates in transistors face challenges in achieving efficient electrical connectivity and reducing parasitic capacitance, while also minimizing the complexity and cost of the fabrication process.
Innovation Solution
The process involves forming Fin Field-Effect Transistors (FinFETs) with the use of metal gates and contact plugs, where low-k gate spacers and high-k dielectric materials are employed to improve isolation and reduce parasitic capacitance, and the metal gates are formed without etching back, eliminating the need for hard masks and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional methods are used to form metal gates with etching back and hard masks, then the fabrication process is well-established, but the process complexity and number of steps increase
Solution Approach 1:
The patent extracts and eliminates the etching back step and hard mask formation from the metal gate fabrication process. By removing these unnecessary intermediate steps, the process is simplified while still achieving the desired metal gate structure formation, directly reducing process complexity and step count
Solution Approach 2:
The patent merges the metal gate formation process with the surrounding fabrication steps by eliminating intermediate etching back and hard mask steps. This integration allows the metal gate to be formed directly in the trench structure without requiring separate etching back and mask removal operations, simplifying the overall manufacturing process
2Reliability
If low-k gate spacers are used to reduce parasitic capacitance, then electrical performance improves, but the fabrication process becomes more complex
Solution Approach 1:
The patent applies low-k gate spacers specifically in the gate region where parasitic capacitance reduction is most critical. By placing this specialized material only where needed (locally) rather than throughout the entire device, the patent achieves improved electrical performance while minimizing the overall complexity of the fabrication process
Solution Approach 2:
The low-k gate spacers serve as an intermediary material between the metal gate and surrounding structures. This intermediate layer provides electrical isolation and reduces parasitic capacitance, acting as a mediator that improves device performance without requiring fundamental changes to the overall device architecture or fabrication approach
3Device complexity
If metal gates are formed without etching back, then the fabrication process is simplified, but precise control of gate dimensions becomes more difficult
Solution Approach 1:
The patent performs preliminary actions by forming the metal gate directly in the trench structure without requiring subsequent etching back. The trench dimensions and metal deposition parameters are carefully controlled in advance to achieve the desired final gate dimensions, eliminating the need for post-deposition dimension adjustment through etching back
Solution Approach 2:
The patent changes the fabrication parameters by eliminating the etching back step and instead controlling gate dimensions through trench formation parameters and metal deposition thickness. This parameter shift from post-processing dimension control to in-process dimension control simplifies the overall process while maintaining manufacturing precision through careful parameter optimization
Data Source
AI summary
A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.