Metal Gate Electrode Unified Memory Cell Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for memory cells require separate processes for forming memory cells and peripheral circuits due to differences in materials, leading to inefficiencies, particularly when using polysilicon electrodes, as they form depletion layers that increase the effective thickness of the gate insulating film, affecting voltage application and data storage.
Innovation Solution
A semiconductor integrated circuit device and method where metal logic gate electrodes, memory gate electrodes, and select gate electrodes are formed using the same metallic material, allowing for a unified manufacturing process that prevents depletion layer formation, thereby reducing the effective thickness of the gate insulating film and enhancing data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon electrodes are used in memory cells, then data storage function is achieved, but depletion layer formation increases effective gate insulating film thickness
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, titanium nitride, or tantalum nitride). This material substitution eliminates depletion layer formation while maintaining the gate's electrical control function, thereby reducing the effective gate insulating film thickness and improving voltage application efficiency.
2Reliability
If separate manufacturing processes are used for memory cells and peripheral circuits, then material-specific requirements are met, but manufacturing complexity and time increase
Solution Approach 1:
The patent makes the metal gate electrode material universal for both memory cell gates and peripheral circuit logic gates. This allows a single manufacturing process to fabricate both memory cells and peripheral circuits simultaneously, eliminating the need for separate processing steps and significantly improving manufacturing efficiency.
3Ease of manufacture
If polysilicon memory gate electrodes are used, then manufacturing is simpler, but voltage application efficiency is reduced due to depletion layer
Solution Approach 1:
The patent changes the gate electrode material from polysilicon to metal, which has superior electrical conductivity and does not form depletion layers. This improves voltage application efficiency and reduces energy consumption during programming and reading operations, while the metal gate can be formed using standard semiconductor manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster operation and reduced voltage requirements for data programming and reading by preventing depletion layer formation, allowing for thinner insulating films and more efficient data storage without the need for separate manufacturing processes for memory cells and peripheral circuits.
Implementation Method 1
a metal memory gate electrode, a metal first select gate electrode, and a metal second select gate electrode can be formed of a metallic material the same as that of a metal logic gate electrode, thereby providing a memory cell that is formed through a series of manufacturing processes of forming the metal logic gate electrode made of a metallic material on a semiconductor substrate
Implementation Method 2
charge is injected into the charge storage layer due to the quantum tunneling effect caused by the voltage difference between the bit voltage and the memory gate voltage
Data Source
Figure 1
Figure 2
Figure 3A~3C
AI summary
A memory cell according to the present invention (1) includes a memory gate structure (2), a first select gate structure (3), and a second select gate structure (4). In the memory gate structure (2), a lower memory gate insulating film (10), a charge storage layer (EC), an upper memory gate insulating film (11), and a metal memory gate electrode (MG) are stacked in this order. The first select gate structure (3) includes a metal first select gate electrode (DG) along a first sidewall spacer (8a) provided on a sidewall of the memory gate structure (2). The second select gate structure (4) includes a metal second select gate electrode (SG) along a second sidewall spacer (8b) provided on another sidewall of the memory gate structure (2). With this configuration, the metal memory gate electrode (MG), the metal first select gate electrode (DG), and the metal second select gate electrode (SG) can be formed of a metallic material the same as that of a metal logic gate electrode (LG11). Thus, the memory cell can be formed through a series of manufacturing processes of forming the metal logic gate electrode (LG1) made of a metallic material on a semiconductor substrate.