Metal Gate Memory Device FinFET Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing high-density flash memory devices with aggressive scaling, particularly in forming memory cells that require precise patterning and materials optimization to maintain performance and reduce manufacturing complexity.
Innovation Solution
The method involves forming semiconductor fins, floating-gate dielectric films, and control gates using photolithography and epitaxial growth, followed by the replacement of polysilicon gates with metal gates to enhance memory cell density and performance, while reducing layout area and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrodes are used in traditional flash memory cells, then the manufacturing process is well-established and reliable, but the device performance and density are limited at decreased feature sizes
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or copper), fundamentally altering the electrical and physical properties to achieve better performance at scaled dimensions while maintaining manufacturing feasibility through adapted deposition and patterning processes
Solution Approach 2:
The patent employs composite gate structures where metal gate electrodes are combined with high-k dielectric materials (such as hafnium oxide or silicon oxynitride) to create a composite gate stack that provides both high performance and manufacturability at advanced technology nodes
2Productivity
If feature sizes are decreased to increase functional density, then more devices can be packed per chip area, but manufacturing precision and pattern formation become more difficult
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional FinFET architectures, where vertical fins provide additional dimensional space for carrier transport and gate control, enabling continued scaling while maintaining manufacturing precision through self-aligned processes
Solution Approach 2:
The patent implements preliminary patterning steps including mandrel formation, spacer deposition, and self-aligned etching processes that pre-establish precise geometric constraints before final gate formation, ensuring manufacturing precision at reduced feature sizes
3Productivity
If metal gate electrodes are used to improve device performance, then performance increases at decreased feature sizes, but manufacturing complexity and process optimization requirements increase
Solution Approach 1:
The patent develops universal metal gate processes that can be applied across multiple device types (logic, memory, RF) and technology nodes, reducing overall manufacturing complexity by using the same metal deposition and patterning tooling for different applications
Solution Approach 2:
The patent introduces intermediary layers such as adhesion barriers, diffusion barriers, and sacrificial mandrels that mediate between the metal gate electrode and underlying structures, simplifying the manufacturing process by decoupling process steps and enabling independent optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory devices with improved performance and reduced manufacturing complexity by optimizing the structure and materials used in memory cell formation, specifically through the use of metal gates and precise patterning techniques.
Implementation Method 1
forming semiconductor fins, floating-gate dielectric films, and control gates using photolithography and epitaxial growth
Data Source
AI summary
A memory device includes a semiconductor fin, a floating gate, a control gate, a source region, an erase gate, and a select gate. The floating gate is above and conformal to the semiconductor fin. The control gate is above the floating gate. The source region is in the semiconductor fin. The erase gate is above the source region and adjacent the control gate. The select gate is above the semiconductor fin. The control gate is between the erase gate and the select gate.