In-Situ Metal Gate Modulators for Low-Resistance Gate Electrodes

The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or copper), which fundamentally alters the electrical properties. Metal gates do not exhibit poly-depletion effects, allowing the effective gate dielectric thickness to be controlled by the physical dielectric thickness alone, thereby enabling reliable inversion layer generation while maintaining a relatively simple gate structure.

The patent employs a composite gate structure consisting of multiple metal layers with different work functions (e.g., a first metal layer with work function Φ1 and a second metal layer with work function Φ2). This composite material approach allows tuning of the overall gate work function to optimize device performance for both NMOS and PMOS transistors, solving the inversion layer generation problem while providing flexibility in device design.

The patent performs preliminary actions by depositing the metal gate layers conformally over the gate dielectric before trench formation. The metal layers are deposited in advance with appropriate thicknesses to account for subsequent trench removal, eliminating the need for complex post-deposition trench filling and CMP processes. This preliminary deposition strategy simplifies the overall fabrication sequence while maintaining adaptability to different device types.

The patent segments the gate formation process into distinct conformal deposition steps for different metal layers, where each layer is deposited independently with controlled thickness. This segmentation allows precise control over the final gate structure geometry and work function characteristics, enabling optimization for both NMOS and PMOS devices without requiring complex integrated processes.

The patent maintains continuous vacuum conditions throughout the metal gate formation process, performing all metal layer depositions, trench formation, and planarization steps without breaking the vacuum. This continuous action prevents oxidation of the gate dielectric and metal layers by excluding atmospheric oxygen, thereby maintaining high reliability of the gate structure while still allowing process flexibility through in-situ process adjustments.

The patent utilizes the vacuum environment as an inert atmosphere throughout the metal gate formation process. By maintaining vacuum conditions, the process creates an oxygen-free environment that prevents oxidation of sensitive layers. This inert environment approach ensures gate dielectric reliability is maintained while providing operational flexibility for process optimization.