Metal Gate Neutral Zone Layout for FinFET Threshold Stability
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Solution Overview
Problem
As integrated circuits (ICs) shrink to meet advanced technology nodes, metal diffusion across the interface between p-type and n-type FinFETs causes undesirable threshold voltage shifts, exacerbating as feature sizes decrease, leading to performance issues.
Innovation Solution
Implementing a neutral zone or metal diffusion barrier in the gate structure between p-type and n-type FinFETs, configured to impede metal diffusion, such as aluminum diffusion, by using a p-type metal layer without an n-type metal layer, thereby preventing unwanted threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal gates of p-type and n-type FinFETs share a common interface to enable different threshold voltages, then device functionality is improved, but metal diffusion across the interface causes threshold voltage variations that worsen as feature sizes shrink
Solution Approach 1:
The gate structure is segmented into three distinct portions: a first metal gate portion for p-type FinFETs, a neutral zone portion, and a second metal gate portion for n-type FinFETs. This segmentation physically separates the metal gates that would otherwise share a common interface, preventing metal diffusion between them while maintaining the ability to provide different threshold voltages for different transistor types.
Solution Approach 2:
A neutral zone portion is introduced as an intermediary element between the first metal gate portion and the second metal gate portion. This neutral zone acts as a barrier that prevents metal diffusion across the interface while allowing the adjacent metal gate portions to maintain their respective functions for p-type and n-type FinFETs.
2Productivity
If IC feature sizes are reduced to increase functional density, then productivity and cost are improved, but metal diffusion effects are exacerbated causing threshold voltage variations
Solution Approach 1:
By segmenting the gate structure into separate portions with a neutral zone in between, the invention prevents metal diffusion that would otherwise be exacerbated at smaller feature sizes. This allows continued scaling to increase functional density while maintaining threshold voltage stability through the physical barrier provided by the neutral zone.
3Manufacturing precision
If a neutral zone is introduced to block metal diffusion, then threshold voltage control is improved, but gate structure complexity increases
Solution Approach 1:
The neutral zone is introduced only in the specific location where metal diffusion occurs between metal gates of adjacent p-type and n-type FinFETs. This localized approach provides the necessary threshold voltage control without adding complexity to the entire gate structure, as the neutral zone is integrated into the existing gate architecture at the critical interface region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces threshold voltage variations between p-type and n-type FinFETs, improving performance by minimizing metal diffusion effects and maintaining desired voltage levels.
Implementation Method 1
the third portion blocks diffusion of metal constituents between the first portion and the second portion
Data Source
AI summary
Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.