Memory Device Metal Gate Sequencing to Prevent NFET WF Oxidation

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Solution Overview

Problem

Conventional IC fabrication methods lead to unintentional oxidation of N-type work function metal in NFET devices, causing performance degradation such as slow device speed and excessive threshold voltage variation, particularly in IC applications like SRAMs where NFET performance is critical.

Innovation Solution

A unique fabrication process flow where P-type WF metal of PFETs is formed before N-type WF metal of NFETs, avoiding exposure of N-type WF metals to oxidation during photoresist removal, thereby preventing performance degradations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional IC fabrication methods are used, then manufacturing simplicity is maintained, but N-type work function metal undergoes unintentional oxidation causing device performance degradation

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the P-type work function metal layer before removing the photoresist layer, thereby establishing a protective configuration in advance that prevents oxidation of the N-type work function metal when the photoresist is subsequently removed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the fabrication process into distinct sequential steps: forming P-type WF metal, removing photoresist, then forming N-type WF metal. This segmentation allows each step to be optimized independently and prevents the oxidation issue by separating the photoresist removal step from the presence of N-type WF metal

Inventive Principle:
Principle #1Segmentation

2Productivity

If photoresist is removed to complete patterning, then manufacturing progress is achieved, but N-type work function metal oxidizes causing threshold voltage variation

Engineering Contradiction:
Improvefabrication progressVSAvoidthreshold voltage consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary action by forming the P-type work function metal layer before photoresist removal, creating a protective structure in advance that prevents oxidation of the N-type work function metal during the necessary photoresist removal step

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The P-type work function metal layer acts as an intermediary protective element that shields the underlying structure during photoresist removal, preventing direct exposure and oxidation of the N-type work function metal while allowing the patterning process to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance by achieving faster device speed and more uniform threshold voltage, particularly in SRAM applications, by protecting the N-type WF metal from oxidation.

Implementation Method 1

a P-type work function (WF) metal layer is deposited over the gate dielectric layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

an N-type WF metal layer is deposited over the P-type WF metal layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS12575172B2Metal gate electrode formation of memory devices
Publication Date: 2026.03.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12575172B2 patent drawing
  • US12575172B2 patent drawing
  • US12575172B2 patent drawing

AI summary

A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.