Multi-Gate Metal Gate Sequencing for NFET Threshold Tuning
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Solution Overview
Problem
Conventional methods for fabricating gate-all-around (GAA) transistors face challenges in depositing work function layers to achieve different threshold voltages due to limited vertical space between channels, particularly affecting n-type field effect transistors (NFETs) in complex IC applications like SRAM devices.
Innovation Solution
The method involves forming n-type work function layers for NFETs before p-type work function layers, allowing p-type layers to fine-tune n-type layers, thereby improving device performance by enabling different threshold voltages for various regions of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function layers are deposited to achieve different threshold voltages for NFETs and PFETs, then device performance is improved, but the vertical space between channels is filled, leaving limited room for threshold voltage tuning
Solution Approach 1:
The patent applies preliminary action by forming the n-type work function layer first, before forming the p-type work function layer. This sequential approach allows the n-type layer to be deposited with adequate vertical space available, enabling proper threshold voltage tuning for NFETs. Subsequently, the p-type work function layer is formed, which automatically fine-tunes the n-type layer's threshold voltage while providing the required p-type characteristics for PFETs. This preliminary sequencing resolves the space constraint by ensuring n-type tuning occurs before the p-type layer occupies the vertical space.
2Ease of manufacture
If conventional fabrication processes are used for GAA transistors, then manufacturing simplicity is maintained, but the ability to fine tune threshold voltage of transistors is limited
Solution Approach 1:
The patent introduces a preliminary sequencing step where n-type work function layers are formed before p-type work function layers in the fabrication process. This maintains compatibility with conventional CMOS processes while adding the critical tuning capability. The n-type layer is deposited first when vertical space is available, enabling threshold voltage fine-tuning for NFETs. The subsequent p-type layer formation automatically provides fine-tuning of the n-type layer, achieving precise threshold voltage control without complicating the overall fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by allowing for precise tuning of threshold voltages, particularly benefiting n-type field effect transistors, thus improving the functionality of complex IC applications such as SRAM devices.
Implementation Method 1
depositing an n-type work function layer on the dielectric layer, the n-type work function layer wrapping around each of the nanostructures in the first stack, depositing a p-type work function layer on the n-type work function layer and over the first and second stacks
Data Source
AI summary
A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.