Metal Gate Spacer Stack for Overlap Capacitance Control
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Solution Overview
Problem
The conventional polysilicon gate in semiconductor devices faces issues such as boron penetration and depletion effects, leading to increased equivalent thickness of the gate dielectric layer and reduced gate capacitance, which affects device performance. Additionally, the overlap capacitance between the gate structure and source/drain region is difficult to control due to the use of materials with higher dielectric constants in spacers and contact etch stop layers.
Innovation Solution
A method involving the formation of a gate structure with a contact etch stop layer (CESL) and interlayer dielectric (ILD) layer, followed by a curing process using ozone and thermal treatment to adjust the oxygen concentration and dielectric constant of these layers, and a replacement metal gate process to transform the gate structure into a metal gate, thereby controlling the overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If materials with higher dielectric constant are used for spacers and contact etch stop layers, then the gate structure can be formed with proper spacing and protection, but the overlap capacitance between gate structure and source/drain region increases and cannot be controlled within desirable range
Solution Approach 1:
The patent applies parameter changes by modifying the dielectric constant of the CESL and ILD layers through a curing process. The curing process transforms the material properties of these layers, reducing their dielectric constants from higher values to lower values that enable proper overlap capacitance control. This parameter transformation resolves the contradiction by allowing the structure to maintain mechanical stability while achieving the desired electrical performance.
2Ease of manufacture
If polysilicon is used as gap-filling material for gate electrode, then the gate structure can be formed, but boron penetration and depletion effects occur leading to increased equivalent thickness of gate dielectric layer and reduced gate capacitance
Solution Approach 1:
The patent extracts the problematic polysilicon material from the gate electrode structure and replaces it with metal materials. By removing the polysilicon layer that causes boron penetration and depletion effects, the invention eliminates the source of gate capacitance degradation while maintaining the gate electrode's structural and functional requirements.
Solution Approach 2:
The patent employs composite materials by combining metal gate electrode materials with high-k dielectric layers. This composite structure replaces the conventional polysilicon gate while incorporating materials with superior electrical properties, achieving both ease of manufacture and improved gate capacitance performance.
3Object-generated harmful factors
If a curing process is performed to adjust oxygen concentration in CESL and ILD layers, then the overlap capacitance is reduced, but the process complexity increases
Solution Approach 1:
The patent merges the curing process with existing fabrication steps by integrating it into the standard process flow after ILD layer formation. The curing process is combined with thermal treatment steps that are already part of the manufacturing sequence, thereby reducing overlap capacitance without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The curing process effectively lowers the overlap capacitance between the gate and source/drain regions, improving device performance by stabilizing the dielectric constants of the CESL, ILD, and spacers, thus enhancing the driving force and overall functionality of the semiconductor device.
Implementation Method 1
performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.