Metal Gate Protection Structure Against Oxidation in SAC Processing

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Solution Overview

Problem

The performance of semiconductor device gates is compromised during processing due to damage, necessitating improved manufacturing techniques for integrated circuits.

Innovation Solution

A semiconductor device structure is fabricated using a fin structure with sacrificial gate structures, sidewall spacers, and a replacement gate sequence, including a gate dielectric layer, gate electrode layer, and self-aligned contact layers, with an isolation layer preventing oxygen diffusion to protect the gate electrode layer from oxidation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional processing methods are used during IC manufacturing, then manufacturing simplicity is maintained, but gate damage and oxidation occur compromising device performance

Engineering Contradiction:
Improvegate performanceVSAvoidgate oxidation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A sacrificial gate structure is introduced as an intermediary protective element during processing. This sacrificial gate serves as a placeholder that protects the underlying channel structure from damage during subsequent processing steps. After the processing is complete, the sacrificial gate is removed and replaced with the actual metal gate, thereby preventing gate oxidation and damage while maintaining manufacturing feasibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The channel structure and gate dielectric are formed in advance before the gate electrode is introduced. This preliminary formation of the channel and dielectric layers allows subsequent processing steps to be performed without exposing the sensitive metal gate to damaging conditions. The gate is installed last, after the structure is ready, preventing oxidation during processing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If gate protection measures are implemented during processing, then gate reliability is improved, but device complexity increases

Engineering Contradiction:
Improvegate stabilityVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate formation process is segmented into distinct phases: first forming the gate dielectric layer, then creating the channel structure, and finally installing the gate electrode. This segmentation allows each component to be optimized independently and protects the gate from damage by ensuring it is present only when needed, reducing overall processing complexity while maintaining reliability

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability and performance of semiconductor device gates by preventing oxidation and maintaining the metal work function, thereby improving the manufacturing process and device stability.

Implementation Method 1

an isolation layer disposed between the gate electrode layer and the first SAC layer... the isolation layer preventing oxygen diffusion to protect the gate electrode layer from oxidation

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS12074111B2Semiconductor devices including metal gate protection and methods of fabrication thereof
Publication Date: 2024.08.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12074111B2 patent drawing
  • US12074111B2 patent drawing
  • US12074111B2 patent drawing

AI summary

Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.