In-Situ Metal Gate Stack Formation to Prevent Oxidation
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Solution Overview
Problem
The poly-depletion effect in conventional polysilicon gates increases the effective gate dielectric thickness, making it difficult to generate an inversion layer in MOS devices, and existing metal gate formation processes face challenges in reducing oxidation and improving reliability.
Innovation Solution
The formation of a metal gate with a work-function layer, a capping layer, and a silicon layer is performed in-situ, without vacuum breaks, to reduce oxidation and enhance the reliability of the gate dielectric, using a process that includes depositing a glue layer on the silicon capping layer to prevent oxidation and improve contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gates are used, then the gate structure is simple to form, but the poly-depletion effect increases the effective gate dielectric thickness making it difficult to generate inversion layer
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or copper), fundamentally altering the electrical properties to eliminate the poly-depletion effect. This material substitution allows the gate to maintain control over the inversion layer without the depletion layer interference that plagues polysilicon gates.
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple metal layers with different work functions. By combining metals with different properties (e.g., a first metal layer with a first work function and a second metal layer with a second work function), the gate can simultaneously optimize performance for both NMOS and PMOS devices, achieving what neither single metal could accomplish alone.
2Reliability
If metal gates with multiple layers are formed to meet different requirements of NMOS and PMOS devices, then device performance is improved, but the formation process becomes complex involving trench removal, multiple metal deposits, and CMP
Solution Approach 1:
The patent performs preliminary actions by forming a dummy gate structure early in the process, then using it as a template for subsequent metal layer deposition. The dummy gate is removed and replaced with metal layers that are deposited conformally over the gate dielectric, simplifying the overall process by establishing a reference structure before the actual metal gate formation.
Solution Approach 2:
The patent introduces a dummy gate as an intermediary structure that facilitates the formation process. The dummy gate serves as a placeholder and template that guides the subsequent metal layer deposition and removal processes, making the complex metal gate formation more manageable and controllable.
3Manufacturing precision
If metal layers are deposited and CMP is performed to form metal gates, then the gate structure is achieved, but oxidation occurs reducing reliability
Solution Approach 1:
The patent employs an inert atmosphere (such as nitrogen or argon) during the metal layer deposition and handling processes to prevent oxidation of the metal layers and gate dielectric. By maintaining an oxygen-free environment, the reliability of the gate structure is preserved while still achieving the desired gate formation precision.
Solution Approach 2:
The patent extracts or removes the source of oxidation by performing processes in a controlled environment where oxygen is excluded. The metal layers are deposited and processed in a vacuum or inert atmosphere, effectively taking out the harmful oxygen from the process environment to prevent oxidation reactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate contact resistance and improves the reliability of the gate dielectric, with a 22% reduction in gate resistance and a 15.9% increase in fluorine diffusion into high-k gate dielectrics, enhancing the overall performance and reliability of the transistors.
Implementation Method 1
the work-function layer, the metal-containing capping layer, the silicon layer, and the glue layer over the silicon layer are in-situ formed, with no vacuum break between the formation processes
Implementation Method 2
a silicon layer is added on top of the work-function layer to reduce the oxidation of the work-function layer
Implementation Method 3
a 15.9% increase in fluorine diffusion into high-k gate dielectrics
Data Source
AI summary
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.