Metal Gate Protection Structure to Prevent Oxidation Damage

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Solution Overview

Problem

The performance of semiconductor device gates is compromised during processing due to damage, necessitating improved manufacturing and processing techniques for integrated circuits.

Innovation Solution

The method involves forming a semiconductor device structure with a fin structure, sacrificial gate structures, sidewall spacers, and replacement gate sequences, including a gate dielectric layer and gate electrode layer, with a metal layer and isolation layer to prevent oxidation of the gate electrode, ensuring the integrity and performance of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional processing methods are used during IC manufacturing, then manufacturing simplicity is maintained, but gate damage and oxidation occur leading to degraded device performance

Engineering Contradiction:
Improvegate integrityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A metal protection layer is deposited over the metal gate electrode before subsequent processing steps. This preliminary protective action prevents oxidation and damage during later manufacturing steps, ensuring gate integrity without requiring complex in-situ protection methods

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal protection layer serves as an intermediary barrier between the metal gate electrode and the harsh processing environment. This intermediate layer prevents direct contact between oxygen and the gate metal, eliminating oxidation issues while maintaining processing simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If metal gate electrodes are exposed during processing, then manufacturing steps are simplified, but oxidation occurs shifting work function and degrading device performance

Engineering Contradiction:
Improveprocessing easeVSAvoidoxidation damage
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The metal protection layer creates an inert environment over the metal gate electrode, preventing oxygen access during processing. This allows subsequent steps to proceed without complex atmosphere control while the gate remains protected from oxidation

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Solution Approach 2:

The metal protection layer is a temporary, sacrificial element that provides protection during processing then is removed. This disposable protective layer is simpler and more effective than attempting to maintain controlled atmospheres throughout manufacturing

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and performance of semiconductor device gates by preventing oxidation and maintaining the metal work function, thereby improving the overall manufacturing process and device performance.

Implementation Method 1

with a metal layer and isolation layer to prevent oxidation of the gate electrode, ensuring the integrity and performance of the semiconductor device

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Data Source

PatentUS20240371773A1Semiconductor devices including metal gate protection and methods of fabrication thereof
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371773A1 patent drawing
  • US20240371773A1 patent drawing
  • US20240371773A1 patent drawing

AI summary

Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, an isolation layer disposed over the gate electrode layer, a first sidewall spacer in contact with the gate dielectric layer, and a liner layer having a first portion disposed between the isolation layer and the gate electrode layer and a second portion in contact with the first sidewall spacer.