Metal Gate Etch-Back Using Filling Regions to Reduce Pattern Loading
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Solution Overview
Problem
The formation of metal gates in FinFETs is hindered by the pattern-loading effect during the etch-back process, leading to uneven recessing of metal gates across different channel lengths, which complicates gap-filling and results in inconsistent gate heights.
Innovation Solution
The introduction of filling regions formed from dielectric materials, such as silicon nitride or polysilicon, which occupy spaces that would otherwise be filled by metal gates, helps to uniformize the gate widths during the etch-back process, reducing the pattern-loading effect and ensuring more consistent gate heights across different channel lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gates are etched simultaneously in a single etch-back process, then the process is simple and fast, but pattern-loading effect causes non-uniform recessing across different channel lengths
Solution Approach 1:
The patent divides the etch-back process into multiple sequential steps, where different channel length transistors are etched in separate processes. This segmentation allows each transistor type to receive optimized etching parameters, eliminating the pattern-loading effect while maintaining overall process efficiency through systematic processing.
Solution Approach 2:
The patent applies different etching conditions to different regions of the wafer based on transistor channel length requirements. By tailoring etching parameters locally for short-channel, mid-channel, and long-channel transistors, the process achieves uniform gate heights across diverse device types while maintaining high productivity.
2Manufacturing precision
If metal gates are formed higher to compensate for hard mask loss, then gate height can be maintained, but gap-filling becomes more difficult
Solution Approach 1:
The patent performs preliminary calculations and adjustments to determine the exact height to which metal gates must be formed above the final level. By pre-calculating the compensation amount for hard mask loss, the process ensures gates are formed to the correct height, making subsequent gap-filling easier and more reliable.
Solution Approach 2:
The patent adjusts deposition parameters during metal gate formation to achieve precise height control. By optimizing deposition rate, temperature, and other parameters, the process forms metal gates at the correct height compensation level, facilitating easier gap-filling while maintaining accurate gate dimensions.
3Device complexity
If pattern-loading effect is not addressed, then the etch-back process remains simple, but some metal gates are recessed more than others
Solution Approach 1:
The patent segments the etch-back process into separate processing steps for different transistor types. This segmentation eliminates the pattern-loading effect by preventing simultaneous etching of different channel length transistors, achieving uniform gate recess while keeping each individual process step relatively simple.
Solution Approach 2:
The patent incorporates monitoring and measurement steps during the etch-back process to track gate height and recess uniformity. By providing feedback about the etching progress and comparing it against target values, the process can adjust parameters in real-time to ensure uniform gate recess across all transistor types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform gate widths and reduced pattern-loading effects, allowing for consistent gate formation and improved manufacturing precision by ensuring that the etch-back process is more uniform across various channel lengths.
Implementation Method 1
the recessing of the hard masks suffers from pattern-loading effect in the etching of the hard masks
Data Source
AI summary
A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.