Metal Gate Plasma Etching for Flatter Semiconductor Gate Profiles
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Solution Overview
Problem
Current reactive ion etching (RIE) processes for semiconductor manufacturing face challenges in achieving precise and efficient etching of gate dielectrics and metal gate electrodes, particularly in forming flat and concave profiles, which affects the integration density and performance of semiconductor devices.
Innovation Solution
A multi-step plasma etching process involving non-zero bias and zero-bias etching steps in the same plasma process apparatus, using gas mixtures like Ar/BCl3/Cl2, is employed to selectively etch gate dielectrics and metal gate electrodes, with the non-zero bias step thinning down the structures and the zero-bias step flattening the top surfaces, allowing for precise control over etch rates and profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RIE process is used for etching gate dielectrics and metal gate electrodes, then the etching process can be performed, but the top surfaces of etched structures exhibit curvature and poor flatness
Solution Approach 1:
The etching process is divided into multiple sequential steps (first etching step, second etching step, third etching step) with different plasma conditions. Each step targets specific portions of the gate structures, allowing progressive flattening of top surfaces while managing process complexity through systematic division of the etching task.
Solution Approach 2:
The patent employs periodic alternation between different plasma bias conditions (zero-bias and non-zero-bias) and different gas compositions throughout the etching sequence. This periodic variation in process parameters enables cyclic flattening and etching actions that progressively improve surface flatness while maintaining control over the overall etching depth.
2Manufacturing precision
If multi-step plasma etching process is used to flatten gate structures, then surface flatness is improved, but the etching process time increases
Solution Approach 1:
Each etching step is designed to perform a specific partial function rather than completing the entire etching task in one step. The first step performs initial etching, the second step flattens specific regions, and the third step completes the etching and flattening. This partial action approach achieves superior flatness by dedicating specific steps to specific functions, accepting increased total time as a trade-off for precision.
Solution Approach 2:
The patent systematically changes plasma parameters (bias voltage, gas composition, pressure) between steps to optimize each etching operation. By adjusting these parameters to match the specific requirements of each etching stage, the process achieves maximum efficiency for each step, minimizing the time required to achieve the desired flatness outcome.
3Productivity
If high density plasma is used for etching, then etching rate increases, but selectivity and anisotropicity control becomes more difficult
Solution Approach 1:
The patent dynamically adjusts plasma conditions by alternating between different bias modes (zero-bias and non-zero-bias) and different gas compositions throughout the etching sequence. This dynamic control allows the process to optimize etching rate during certain steps while achieving superior selectivity and anisotropicity during flattening steps, adapting the plasma characteristics to the specific requirements of each etching stage.
Solution Approach 2:
The patent employs systematic parameter changes by varying plasma power, pressure, gas composition, and bias voltage between different etching steps. These parameter adjustments enable the process to achieve high etching rates when needed while maintaining precise selectivity and anisotropicity control during flattening operations, resolving the contradiction between productivity and precision through controlled parameter variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate structures with reduced curvature and improved flatness, enhancing the integration density and performance of semiconductor devices by precisely controlling the etching process, thereby addressing the limitations of existing RIE methods.
Implementation Method 1
physical bombardment by ions
Implementation Method 2
chemical etching by radicals
Implementation Method 3
surface passivation by the deposition of passivating films
Data Source
AI summary
A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.