Metal Gate Interconnect Structure With Void-Free Bottom-Up Plug Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with narrow dimensions face increased resistivity and void formation due to high aspect ratios of metal liners and barrier layers, which can lead to manufacturing inefficiencies and increased costs.
Innovation Solution
Implementing a bottom-up metal-on-metal deposition method that eliminates the need for metal liners and barrier layers by directly depositing metal plugs on a metal cap within a recess, using area-selective thin film deposition techniques like chemical vapor deposition or atomic layer deposition to fill the recess without voids and reduce resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal liners and barrier layers are used in narrow interconnect structures, then manufacturing complexity increases and void formation occurs, but electrical connectivity is maintained
Solution Approach 1:
The patent removes metal liners and barrier layers from the interconnect structure, retaining only the essential copper plug and dielectric layers. This extraction eliminates the complex multi-layer metal structure while maintaining electrical functionality through direct copper-to-dielectric interfaces and benzocyclobutene integration.
Solution Approach 2:
The patent merges the dielectric layer and barrier function into a single integrated structure using benzocyclobutene material that serves both as dielectric insulation and as a native barrier to copper diffusion, eliminating the need for separate metal liner and barrier layers.
2Area of stationary object
If recess width is reduced to increase device density, then resistivity increases due to high aspect ratios, but device miniaturization is achieved
Solution Approach 1:
The patent changes the material parameters by using copper plugs with optimized dimensions and benzocyclobutene dielectric properties that maintain low resistivity even in narrow recesses. The copper plug width and height are specifically controlled to achieve aspect ratios that prevent void formation while maintaining electrical conductivity.
Solution Approach 2:
The patent uses a simplified interconnect structure that copies only the essential functional elements (copper plug, dielectric, benzo layer) without replicating the complex metal liner and barrier layer structures, thereby reducing manufacturing steps while maintaining electrical performance.
3Productivity
If area-selective deposition is used to eliminate metal liners, then manufacturing time is reduced, but deposition precision requirements increase
Solution Approach 1:
The patent introduces benzocyclobutene as an intermediary material that self-limits copper deposition through its chemical properties, eliminating the need for precise metal liner thickness control. The benzo layer acts as a natural barrier that stops copper diffusion without requiring ultra-precise deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced recess width while maintaining low resistivity, decreasing manufacturing time and costs, and enhancing the semiconductor device's performance by eliminating voids and nucleation layers.
Implementation Method 1
performing a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap
Implementation Method 2
using area-selective thin film deposition techniques like chemical vapor deposition or atomic layer deposition to fill the recess without voids
Implementation Method 3
using area-selective thin film deposition techniques like chemical vapor deposition or atomic layer deposition to fill the recess without voids
Data Source
AI summary
In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.