Metal Gate Height Tuning for PUF Threshold Voltage Mismatch
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Solution Overview
Problem
Current software-based security measures in IoT devices are insufficient to protect against hardware-level threats, such as remote control and data theft from counterfeit chips, necessitating a hardware-based security solution.
Innovation Solution
A semiconductor process that controls metal gate heights through chemical mechanical planarization (CMP) to create threshold voltage mismatching, enabling random code generation in physically unclonable functions (PUF) for unique IC fingerprints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If software-based security measures are used in IoT devices, then ease of implementation is improved, but security reliability against hardware-level threats deteriorates
Solution Approach 1:
The patent introduces a physically unclonable function (PUF) based on metal gate height variations as an intermediary layer between software security protocols and hardware threats. The PUF generates unique fingerprints based on uncontrollable manufacturing variations in metal gate heights, providing hardware-level security without requiring complex hardware security modules. This intermediary mechanism enables software-based security systems to achieve hardware-level protection through standardized semiconductor manufacturing processes.
2Manufacturing precision
If metal gate heights are controlled through CMP process to create threshold voltage mismatching, then uniqueness of IC fingerprints is improved, but manufacturing precision control becomes more difficult
Solution Approach 1:
The patent converts the harmful effect of uncontrollable manufacturing variations and CMP process inconsistencies into a beneficial feature. Instead of attempting to eliminate variations in metal gate heights, the invention deliberately exploits these variations to create unique threshold voltage characteristics for each IC. The uncontrollable manufacturing imprecision becomes the source of unclonable fingerprints, transforming a process challenge into a security advantage.
Solution Approach 2:
The patent changes the focus from controlling metal gate height to a fixed value to measuring and utilizing the distribution of threshold voltages that result from varying gate heights. By shifting the parameter of interest from the physical dimension (gate height) to the electrical characteristic (threshold voltage), the system can achieve high uniqueness without requiring precise control of the manufacturing process.
3Reliability
If metal gate heights are reduced below critical gate height, then threshold voltage mismatching increases improving PUF performance, but transistor drive current decreases
Solution Approach 1:
The patent applies local quality by creating regions with different metal gate heights within the same device structure. Specifically, it uses selective removal of metal gates in certain regions to create local threshold voltage variations, while maintaining adequate gate heights in other regions to preserve drive current. This spatial differentiation allows the device to simultaneously achieve high PUF performance through local mismatching and adequate power efficiency through overall sufficient gate dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances hardware security by producing unique and unpredictable IC fingerprints, reducing duplication risks and improving resistance to environmental variations, thus bolstering IoT device security.
Implementation Method 1
performing a chemical mechanical planarization process to remove the metal filling layer, thereby forming metal gates and make heights of the metal gates lower than a critical gate height
Implementation Method 2
a local threshold voltage mismatching of the PIO pair becomes larger since the heights of metal gates are lower than the critical gate height, so as to achieve random code generation in physically unclonable function
Data Source
AI summary
A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).