Metal Gate Recess and Cap for IC Isolation
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Solution Overview
Problem
In integrated circuit manufacturing, metal residue left on the surface after planarization processes can lead to unwanted conductive paths between adjacent contacts, causing failures and rejection of ICs during high-voltage stress tests, due to the difficulty in completely removing metal residue and the trapping of residue between subsequent layers.
Innovation Solution
A method involving etching to recess the metal gate below the surface of the inter-layer dielectric, followed by forming a metal cap with a different composition and thickness of approximately 0.5 to 5 nanometers, which is then covered by dielectric cap layers to create a structure that allows for electrical contacts while preventing unwanted conductive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If planarization process is used to flatten the surface, then surface flatness is improved, but metal residue remains on the surface causing unwanted conductive paths
Solution Approach 1:
The patent extracts the harmful metal residue from the surface by performing a selective etch process that removes only the metal gate material at the surface level, while leaving the underlying structure intact. This extraction eliminates the source of unwanted conductive paths without affecting the overall planarization achieved by CMP.
Solution Approach 2:
The patent applies preliminary anti-action by forming a sacrificial metal layer before the final planarization step. This sacrificial layer is designed to be selectively removed in a subsequent etch process, preventing the metal residue problem from occurring in the first place by counteracting the harmful effect of metal contamination during planarization.
2Productivity
If metal residue is trapped between subsequent layers, then manufacturing process continues, but electrical isolation between contacts is compromised
Solution Approach 1:
The patent performs preliminary action by etching away potential metal residue sources before subsequent dielectric layers are deposited. By removing the metal gate surface material in advance, the patent prevents metal residue from being trapped between layers, thereby maintaining electrical isolation between contacts while keeping the manufacturing process flowing without interruptions for additional cleaning steps.
3Area of moving object
If contacts are placed in close proximity, then circuit density is improved, but unwanted conductive paths between contacts increase
Solution Approach 1:
The patent extracts the harmful metal residue that could create unwanted conductive paths between closely spaced contacts. By selectively removing metal gate material at the surface through etching before depositing dielectric layers, the patent eliminates the contamination source that would otherwise bridge adjacent contacts, enabling higher circuit density without compromising electrical isolation.
4Device complexity
If conventional cleaning steps are used after planarization, then manufacturing process is simple, but metal residue cannot be completely removed
Solution Approach 1:
The patent replaces mechanical cleaning methods with a chemical etching process that selectively removes metal gate material. Instead of relying on mechanical abrasion or chemical-mechanical polishing to remove metal residue, the patent uses a targeted wet or vapor HF etch that chemically dissolves the metal gate surface material, achieving complete residue removal with a simple, selective chemical process rather than complex mechanical cleaning systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces failures due to metal residue, enhances electrical isolation, and improves the reliability of integrated circuits by ensuring that the metal cap covers the recessed metal gate, preventing metal oxidation and gouging issues during manufacturing.
Implementation Method 1
etching to recess the metal gate below the surface of the inter-layer dielectric
Implementation Method 2
preventing metal oxidation and gouging issues during manufacturing
Data Source
AI summary
This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.