Metal Gate Recess via Selective Etching
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Solution Overview
Problem
Current methods for forming a recessed gate structure using tungsten in semiconductor devices are expensive and time-consuming, involving chemical mechanical polishing (CMP) and reaction ion etch (RIE) processes, which result in reduced metal contact and increased resistance due to uniform polishing of liner and metal layers.
Innovation Solution
A method involving the application of a liner and metal layer in a trench, followed by separate etching of these layers using a single chamber, with the liner layer etched back further than the metal layer, and subsequent bottom-up fill/growth of metal within the trench to form a metal gate recess, eliminating the need for CMP and RIE processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMP and RIE processes are used to form a recessed gate structure, then the gate structure can be formed, but the process becomes expensive and time-consuming
Solution Approach 1:
The patent combines the CMP process and RIE process into a single integrated recess formation step. The recess is formed by etching through the gate metal layer and gate dielectric layer together in one process, eliminating the need for separate CMP and RIE steps, thus reducing process time and cost while maintaining the recessed gate structure.
Solution Approach 2:
The patent segments the gate structure into distinct layers (gate metal layer and gate dielectric layer) that are etched to different depths. The gate metal layer is etched deeper than the gate dielectric layer, creating the recessed structure. This selective etching allows the recess to be formed in a single process step rather than requiring multiple sequential steps.
2Reliability
If CMP and RIE processes are used to form a recessed gate structure, then the gate structure can be formed, but the process becomes costly
Solution Approach 1:
The patent merges CMP and RIE into a single recess formation process, reducing the number of expensive equipment uses and process steps. This integration lowers manufacturing costs by eliminating the need for separate CMP and RIE tool rentals or equipment purchases, while still achieving the required recessed gate structure.
3Device complexity
If liner layer and gate metal are recessed evenly, then the recess structure is simple, but metal contact area is reduced and resistance increases
Solution Approach 1:
The patent applies local quality by creating different recess depths for different layers. The gate metal layer is etched to a greater depth than the gate dielectric layer, creating a stepped recess structure. This allows the metal contact area to be enlarged at the bottom of the recess while maintaining the overall recess structure, thereby reducing electrical resistance without excessive complexity.
4Reliability
If separate etching of liner layer and metal layer is performed, then metal contact area increases and resistance decreases, but process complexity increases
Solution Approach 1:
The patent combines separate etching steps into a single integrated etching process that simultaneously etches both the gate metal layer and gate dielectric layer to different depths. This is achieved through proper process parameter optimization and selective etching, allowing the complex differential etching to be performed in one step rather than requiring multiple sequential etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and increases metal contact area, making the process less costly and improving device performance by allowing for larger grains and lower resistance, while also simplifying the workflow by using a single etching tool.
Implementation Method 1
a liner layer and a metal layer (e.g., W) will be applied in a trench (e.g., via CVD)
Implementation Method 2
performing a first etch to etch at least a portion of the metal layer in the trench; performing a second etch to etch at least a portion of the liner layer
Implementation Method 3
a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench
Data Source
AI summary
Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.