Metal Gate Work Function Control via Thermal Reflow
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving proper work functions for n-type (NMOS) and p-type (PMOS) metal gates in CMOS devices, as existing methods require separate metal layers, which are not satisfactory in all respects and increase complexity and costs.
Innovation Solution
A method for fabricating semiconductor devices involves forming high-k dielectric layers and metal gates with specific work functions by creating trenches, depositing barrier and metal layers, and performing thermal reflow processes to achieve the necessary work functions for NMOS and PMOS devices without the need for separate N-metals and P-metals, simplifying the process and reducing the risk of void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate metal layers are used to achieve different work functions for PMOS and NMOS metal gates, then the work function requirements are met, but the processing complexity and manufacturing costs increase
Solution Approach 1:
The patent merges the formation of different work function metal layers into a single unified process. A dummy gate structure is formed that includes both N-type work function metal and P-type work function metal in an integrated manner, eliminating the need for separate metal layer deposition processes for each device type. This consolidation reduces processing steps while maintaining the ability to provide appropriate work functions for both PMOS and NMOS devices.
Solution Approach 2:
The patent performs preliminary action by forming the dummy gate structure with integrated work function metals before the actual gate formation. The dummy gate is created in advance with the appropriate metal composition, and then selectively removed to reveal the pre-prepared work function metals. This preliminary preparation simplifies subsequent processing steps and reduces overall manufacturing complexity.
2Reliability
If separate metal layers are used for PMOS and NMOS gates, then proper work functions are achieved, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple metal deposition operations into a single integrated dummy gate formation process. By forming both N-type and P-type work function metals within one dummy gate structure using unified processing steps, the patent reduces the number of deposition chambers, processing time, and material waste, thereby lowering manufacturing costs while maintaining proper work function characteristics for both device types.
Solution Approach 2:
The dummy gate structure serves multiple functions simultaneously: it provides the work function metals for both PMOS and NMOS devices, acts as a placeholder during subsequent processing, and enables selective removal to reveal the appropriate work function metals. This multi-functionality eliminates the need for separate processing lines for different device types, reducing manufacturing complexity and cost.
3Productivity
If advanced technology nodes are used to reduce geometry size, then functional density increases, but the risk of void formation in metal gates increases
Solution Approach 1:
The patent performs preliminary action by forming the dummy gate structure with integrated work function metals before the actual gate formation. The dummy gate is created in advance with the appropriate metal composition, and then selectively removed to reveal the pre-prepared work function metals. This preliminary preparation simplifies subsequent processing steps and reduces overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of metal gates with proper work functions, improving device performance and reliability while reducing processing complexity and costs by eliminating the need for separate metal layers, and enhancing fill margin and void prevention in advanced technology nodes.
Implementation Method 1
performing a thermal process to reflow the second metal layer
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).