Metal Gate Fabrication via Replacement Process for Uniformity
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Solution Overview
Problem
The existing semiconductor device fabrication methods using metal gates face challenges in achieving uniformity and target characteristics due to non-uniform surfaces after heat treatment, which complicates the formation of metal gate structures.
Innovation Solution
The method involves forming inter-metal dielectric layers with trenches, depositing dielectric and conductive layers, followed by heat treatment and removal of capping and conductive layers to create uniform metal gate structures with specific work function adjustment layers, ensuring uniformity and target characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is performed on the substrate after forming conductive layers, then the electrical characteristics and work function of the metal gate structure are improved, but the surface becomes non-uniform which complicates subsequent metal gate formation
Solution Approach 1:
The patent performs heat treatment before forming the metal gate structure to establish the desired electrical characteristics and work function. By conducting the heat treatment at an earlier stage, the substrate and underlying layers are pre-conditioned with the necessary electrical properties before the metal gate deposition process begins, ensuring both electrical performance and surface readiness for subsequent steps.
Solution Approach 2:
The patent introduces an intermediary layer between the substrate and the metal gate structure. This intermediate layer serves as a buffer that maintains surface uniformity while allowing the heat treatment to achieve the desired electrical characteristics. The intermediary layer decouples the conflicting requirements of electrical optimization and surface flatness.
2Manufacturing precision
If multiple layers with different thicknesses are formed to achieve precise work function adjustment, then the work function precision is improved, but the process complexity increases
Solution Approach 1:
The patent applies local quality by forming conductive layers with spatially varying thicknesses in different regions of the substrate. By controlling the thickness of conductive layers locally, the work function can be precisely adjusted for different device regions without requiring uniform thick layers everywhere, thus achieving precise work function control while avoiding the need for excessively complex multi-layer structures.
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness of conductive layers as a control parameter for work function adjustment. Instead of adding multiple distinct material layers, the invention changes the physical parameter (thickness) of existing conductive layers to achieve the desired work function precision, thereby simplifying the overall process while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of uniform metal gate structures with precise work function adjustments, improving the semiconductor device's performance and characteristics.
Implementation Method 1
performing a heat treatment after the first and second capping layers have been formed
Implementation Method 2
forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench
Data Source
AI summary
A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.