Metal Gate SAC Profile Shaping to Prevent FinFET Contact Shorting
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Solution Overview
Problem
Aggressive scaling down of IC dimensions in FinFETs leads to increased leakage current and shorting between the FinFET gate and source/drain regions, degrading device performance, with existing self-aligned contact (SAC) fabrication methods struggling to precisely land source/drain contact metal without shorting to the metal gate via.
Innovation Solution
A method involving a plasma treatment to modify the profile of the self-aligned contact hard mask (SAC HM) layer, creating a larger width at the top and smaller width at the bottom of the opening, followed by a chemical mechanical polishing (CMP) process to ensure precise landing of the source/drain contact metal and prevent shorting, using a fluorine-based plasma treatment and subsequent deposition of a SAC HM layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling down of IC dimensions is performed in FinFETs, then production efficiency and cost are improved, but leakage current increases and shorting between gate and source/drain regions occurs, degrading device performance
Solution Approach 1:
The patent applies local quality by creating a tapered profile in the SAC HM layer where the width varies along the vertical direction - wider at the top and narrower at the bottom. This localized variation in geometry provides different functional characteristics at different heights: the narrower bottom portion prevents shorting while the wider top portion ensures proper metal landing, thus resolving the contradiction between scaling benefits and device reliability.
Solution Approach 2:
The invention introduces asymmetry in the SAC HM layer structure by forming a non-uniform width profile along the vertical axis. The layer transitions from a smaller width at the bottom to a larger width at the top, creating an asymmetric geometry that simultaneously achieves gap prevention at the critical interface and adequate contact area at the upper level, thereby maintaining device performance during aggressive scaling.
2Ease of manufacture
If conventional SAC fabrication methods are used, then manufacturing simplicity is maintained, but precise landing of source/drain contact metal becomes difficult, causing shorting to metal gate via
Solution Approach 1:
The patent implements preliminary action by pre-forming the tapered SAC HM layer profile before depositing the source/drain contact metal. This pre-established geometric configuration with controlled width variation guides the subsequent metal deposition process, ensuring that the contact metal lands precisely in the intended region without shorting to the gate via, thus improving manufacturing precision while maintaining process integration.
Solution Approach 2:
The invention applies parameter changes by modifying the geometric parameters of the SAC HM layer, specifically the width dimension along the vertical axis. By controlling the width to vary from bottom to top, the process creates a profile that optimizes both the gap prevention function and the metal landing function, thereby achieving precise contact metal placement without compromising manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances device performance by improving the etching window for source/drain contact metal landing and preventing shorting between the metal gate via and source/drain contact, thereby improving device reliability and performance.
Implementation Method 1
performing a plasma treatment process to modify a profile of the opening
Implementation Method 2
chemical mechanical polishing (CMP) process to ensure precise landing
Data Source
AI summary
A method of forming a semiconductor device includes providing a device having a gate stack with a metal gate layer and a spacer layer disposed on a sidewall of the gate stack. In some embodiments, the method further includes performing an etch-back process to the metal gate layer to form an opening over the gate stack. In various examples, the method further includes performing a plasma treatment process to modify a profile of the opening. In some cases, the method further includes forming a HM layer over the metal gate layer and within the opening having the modified profile.