Metal Gate Stack Formation with Sealed Recesses
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing efficiency.
Innovation Solution
The process involves forming FinFET structures with fins patterned using photolithography and self-aligned processes, such as double-patterning or multi-patterning, and subsequent steps like epitaxial growth, spacer formation, and replacement of dummy gate stacks with metal gate stacks, along with the deposition and planarization of various layers to create a semiconductor device structure that enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but processing and manufacturing complexity increases
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (double-patterning or multi-patterning) where the gate pattern is formed in stages. First, a mandrel is formed and spacers are deposited and etched to create the final gate pattern. This segmentation allows achievement of smaller feature sizes with controlled complexity at each step rather than attempting to pattern directly at the final dimensions.
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures to define the eventual gate pattern. These mandrels serve as templates around which spacers are formed, and the mandrels are removed after spacer formation. This preliminary action enables precise pattern transfer while simplifying the actual gating structure formation process.
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area utilization is improved, but fabrication difficulty increases
Solution Approach 1:
Spacer materials serve as intermediaries that transfer the pattern from the mandrel to the final gate structure. The spacers are deposited conformally over the mandrels and then anisotropically etched to create the gate pattern. This intermediary approach enables precise pattern definition at small dimensions while using standard deposition and etching processes.
Solution Approach 2:
The patent replaces direct photolithographic patterning at small dimensions with a self-aligned spacer formation process. Instead of relying on increasingly difficult direct patterning at sub-10nm dimensions, the process uses conformal film deposition and anisotropic etching which are more controllable and manufacturable at advanced nodes.
3Ease of manufacture
If conventional gate structures are used at smaller sizes, then manufacturing is simpler, but device reliability deteriorates
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to metal materials (such as tungsten, cobalt, or copper). This parameter change enables better electrical characteristics and reliability at small dimensions while maintaining compatibility with the spacer-based patterning process. The metal gate materials provide superior mobility and reduced variability compared to polysilicon at advanced nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of reliable semiconductor devices with improved performance and reduced parasitic capacitance, leading to enhanced device reliability and power consumption efficiency.
Implementation Method 1
forming FinFET structures with fins patterned using photolithography
Implementation Method 2
subsequent steps like epitaxial growth
Data Source
AI summary
A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The spacer element has an inner spacer and a dummy spacer, and the inner spacer is between the dummy spacer and the dummy gate stack. The method also includes forming a dielectric layer to surround the spacer element and the dummy gate stack and replacing the dummy gate stack with a metal gate stack. The method further includes removing the dummy spacer of the spacer element to form a recess between the inner spacer and the dielectric layer. In addition, the method includes forming a sealing element to seal the recess such that a sealed hole is formed between the metal gate stack and the dielectric layer.