Replacement Metal Gate Recessing With Selective Deposition Control
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Solution Overview
Problem
The formation of metal gates in MOS devices often results in gate loss due to excessive thinning of inter-layer dielectric during the etch-back processes, which complicates the formation of both long-channel and short-channel FinFETs, requiring separate etch-back processes and leading to unpredictability in gate contact openings.
Innovation Solution
The process involves forming a dummy gate stack, etching back a protection layer to expose the metal-containing layers, and selectively depositing metal layers to form replacement gates, which avoids the need for full filling and subsequent planarization, thereby preventing gate-height loss and ensuring a homogenous metal material in gate contact openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple etch-back processes are performed to recess metal gates for long-channel and short-channel devices separately, then the loading effect is reduced, but the inter-layer dielectric is thinned excessively causing gate loss
Solution Approach 1:
A protection layer is deposited over the inter-layer dielectric before the etch-back process. This protection layer serves as a sacrificial layer that prevents excessive etching of the inter-layer dielectric during metal gate recessing. The protection layer is selectively removed after the etch-back is complete, revealing the recessed metal gates without gate loss.
Solution Approach 2:
The protection layer acts as an intermediary between the etching process and the inter-layer dielectric. It absorbs the excessive etching action that would otherwise damage the inter-layer dielectric, allowing the etch-back to proceed without causing gate loss while still achieving the desired metal gate recess.
2Reliability
If separate etch-back processes are used for long-channel and short-channel devices, then loading effect is reduced, but process complexity increases
Solution Approach 1:
The protection layer approach allows both long-channel and short-channel device etch-back processes to be merged into a single unified process. The protection layer protects both device types simultaneously, eliminating the need for separate processing steps while maintaining the benefits of selective recessing.
Solution Approach 2:
The protection layer serves multiple functions: it protects the inter-layer dielectric from excessive thinning, enables simultaneous processing of different device types, and provides a uniform reference plane for etch-depth control across all devices.
3Shape
If CMP is used to planarize after metal layer deposition, then surface flatness is improved, but gate-height loss occurs due to inter-layer dielectric thinning
Solution Approach 1:
The mechanical CMP process is replaced with a chemical deposition approach. Instead of mechanically removing material to achieve flatness, a protection layer is chemically deposited to provide a uniform surface. This substitution eliminates the material removal that causes gate-height loss while achieving the desired surface flatness.
Solution Approach 2:
The process transitions from material removal (CMP) to material addition (deposition). By changing the fundamental parameter from subtractive to additive manufacturing, the process achieves surface flatness without removing the inter-layer dielectric, thereby preventing gate-height loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents gate-height loss by avoiding excessive inter-layer dielectric thinning and ensures predictable, controlled metal deposition, simplifying the formation of FinFETs with consistent metal exposure in gate contact openings.
Implementation Method 1
etching back a protection layer to expose the metal-containing layers
Implementation Method 2
selectively depositing metal layers to form replacement gates
Data Source
AI summary
A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.