Metal Gate Stack Structure for Selective Etch-Back in FinFETs
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to form reliable semiconductor devices at increasingly smaller sizes, as the scaling-down process complicates processing and manufacturing due to decreased feature sizes.
Innovation Solution
The process involves forming FinFET structures with fins patterned using photolithography and self-aligned processes, followed by the formation of dummy gate stacks, spacer elements, and epitaxial source/drain features. The gate dielectric layer and work function layer are then deposited and etched back to form a metal gate stack, with a low-temperature etching back process ensuring high selectivity and protecting spacer elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but processing complexity and manufacturing difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple functional layers including gate dielectric layer, first metal layer, second metal layer, and third metal layer. Each layer serves a specific function and can be independently processed, allowing complex functionality to be achieved through modular construction rather than monolithic structures
Solution Approach 2:
Different metal layers are used at different locations within the gate stack to provide locally optimized properties. The first metal layer provides gate conductivity, the second metal layer provides work function tuning, and the third metal layer provides additional functionality. This local differentiation allows precise control of electrical characteristics while managing processing complexity
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but manufacturing precision requirements increase
Solution Approach 1:
A gate dielectric layer is formed on the semiconductor substrate before the metal layers are deposited. This preliminary dielectric layer serves as a foundation that defines the gate region boundaries and provides electrical isolation, establishing precise geometric constraints before subsequent metal deposition steps
Solution Approach 2:
The gate dielectric layer acts as an intermediary between the semiconductor substrate and the metal gate layers. It provides a well-defined interface that controls the positioning and thickness of subsequent metal layers, thereby maintaining manufacturing precision through a mediating layer that buffers dimensional control
3Reliability
If multi-layer metal gate stack is formed to improve device performance, then device reliability is improved, but device complexity increases
Solution Approach 1:
The multi-layer metal gate stack performs multiple functions simultaneously: the first metal layer provides primary gate conductivity, the second metal layer adjusts work function to control threshold voltage, and the third metal layer provides additional electrical or structural functionality. This multi-functionality within a single integrated structure improves device reliability without requiring separate components
Data Source
AI summary
A semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer, and the gate dielectric layer has a curved sidewall and a vertical sidewall. The semiconductor device structure also includes a protection element over the metal gate stack, and the protection element extends conformally along the curved sidewall and the vertical sidewall to reach a topmost surface of the work function layer. The semiconductor device structure further includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure, and the topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than the topmost surface of the work function layer.