Multi-Layer Metal Gate Semiconductor Structure

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Solution Overview

Problem

Conventional polysilicon gates in semiconductor devices face challenges as they scale down, necessitating the development of superior semiconductor structures with metal gates for improved performance and reliability.

Innovation Solution

A semiconductor structure comprising an isolation layer, gate dielectric layer, and multiple work function metals with barrier layers, along with a manufacturing method that forms these layers in a specific sequence to enhance filling capacity and integrity, resulting in improved performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional polysilicon gates are used in scaled-down semiconductor devices, then manufacturing process is simpler, but device performance and reliability deteriorate

Engineering Contradiction:
Improvedevice performance and reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate structure is segmented into multiple functional layers: gate dielectric layer, first work function metal layer, first bottom barrier layer, second work function metal layer, and first top barrier layer. Each layer serves a specific function, allowing optimization of device performance while managing manufacturing complexity through modular deposition processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure employs composite materials combining high-K dielectric materials with multiple metal layers having different work functions and barrier properties. This composite approach enables superior electrical performance and reliability compared to conventional polysilicon gates.

Inventive Principle:
Principle #40Composite materials

2Reliability

If metal gates with multiple layers are implemented, then device performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice performanceVSAvoidlayer formation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate dielectric layer is formed first as a preliminary step, providing a stable foundation for subsequent metal layer depositions. Each metal layer is deposited sequentially with controlled thicknesses, ensuring precise thickness control and interface quality before proceeding to the next layer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent optimizes deposition parameters such as thickness, composition, and deposition conditions for each layer. By carefully controlling these parameters, the manufacturing process achieves the required precision for multi-layer metal gates while maintaining device performance.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If filling metal is used to replace polysilicon, then superior filling capacity is achieved, but maintaining intact integrity becomes challenging

Engineering Contradiction:
Improvefilling capacityVSAvoidfilling metal integrity
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

Barrier layers are introduced as intermediary layers between the filling metal and adjacent structures. These barrier layers prevent unwanted diffusion and interactions, maintaining the integrity of the filling metal while enabling superior filling capacity in the gate structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure combines filling metal with barrier layers and work function metals in a composite configuration. This composite approach allows the filling metal to provide superior filling capacity while the barrier layers preserve its structural integrity and prevent degradation.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS9231071B2Semiconductor structure and manufacturing method of the same
Publication Date: 2016.01.05 STELLAR SEMICONDUCTOR JAPAN GK
  • US9231071B2 patent drawing
  • US9231071B2 patent drawing
  • US9231071B2 patent drawing

AI summary

A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.