Metal Gate Semiconductor Devices with Deposition Insulating Layer
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Solution Overview
Problem
As feature sizes of metal oxide semiconductor (MOS) transistors decrease, there is a need to increase capacitance between the gate and channel while improving operating characteristics, and the conventional silicon oxide film faces physical limitations in electrical properties, leading to the exploration of high-k films and the replacement of polysilicon gate electrodes with metal gate electrodes.
Innovation Solution
The use of a deposition insulating layer in semiconductor devices to prevent residue formation during fabrication, combined with a high-k gate insulating layer and a metal gate structure, which includes a trench formation and sequential layering of deposition insulating, gate insulating, and metal gate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the thickness of silicon oxide film is reduced to maintain small equivalent oxide film thickness, then leakage current increases, but using high-k film maintains electrical properties while reducing leakage current
Solution Approach 1:
The patent employs a composite gate insulating film structure consisting of a first insulating film (silicon oxide or silicon oxynitride) and a second insulating film (high-k material such as hafnium oxide, zirconium oxide, or tantalum oxide). This composite structure combines the advantages of both materials: the silicon-based film provides good interface characteristics and the high-k film provides high dielectric constant, thereby achieving low leakage current while maintaining reliable electrical properties.
2Reliability
If polysilicon gate electrode is replaced with metal gate electrode, then resistance decreases and operating characteristics improve, but fabrication process complexity increases
Solution Approach 1:
The patent introduces a deposition insulating layer formed by chemical vapor deposition (CVD) before forming the metal gate electrode. This preliminary action serves multiple purposes: it prevents residue generation from sacrificial layer removal, provides a clean interface for metal gate formation, and simplifies the overall fabrication process by eliminating the need for complex residue removal steps.
3Ease of manufacture
If conventional fabrication process is used without deposition insulating layer, then process is simpler, but residue is generated during sacrificial layer removal
Solution Approach 1:
The patent introduces a deposition insulating layer as an intermediary between the sacrificial insulating layer and the gate insulating layer. This intermediary layer is formed by CVD and can be easily removed without leaving residue, thereby solving the residue problem while maintaining process simplicity. The deposition insulating layer acts as a mediator that facilitates clean removal and prevents contamination of subsequent layers.
4Reliability
If silicon oxide film is used as gate insulating film, then interface characteristics are good, but capacitance is limited and operating characteristics deteriorate at small feature sizes
Solution Approach 1:
The patent uses a composite gate insulating film structure where a silicon-based insulating film (first insulating film) is combined with a high-k insulating film (second insulating film). The silicon-based film maintains excellent interface characteristics with the semiconductor substrate, while the high-k film increases the capacitance, thereby improving operating characteristics at small feature sizes without sacrificing interface quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating characteristics of MOS transistors by reducing leakage current and improving breakdown voltage, while allowing for easier residue removal and compatibility with non-silicon substrates, thus addressing the limitations of conventional silicon oxide films and polysilicon gate electrodes.
Implementation Method 1
forming a deposition insulating layer in the trench to be disposed on the field insulating layer
Implementation Method 2
research into a high-k film having a high dielectric constant is actively being conducted. The high-k film may reduce leakage current between a gate electrode and a channel region
Data Source
AI summary
Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.