Metal Gate Semiconductor Device Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing contact resistance and minimizing the number of lithography operations while manufacturing semiconductor devices with non-volatile memory cells and peripheral logic circuits, particularly due to height differences in interlayer dielectric layers affecting chemical mechanical polishing performance.
Innovation Solution
A method is introduced where a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas, allowing for the formation of isolation insulating layers and subsequent polysilicon layers, followed by the replacement of polysilicon layers with metal materials for the erase and select gates, reducing resistance and minimizing lithography operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polysilicon layers are used for gates in nanometer technology processes, then device density and integration are improved, but contact resistance increases
Solution Approach 1:
The patent changes the material parameter of the gate from polysilicon to metal (such as tungsten, cobalt, or copper), fundamentally altering the electrical properties to achieve lower contact resistance while maintaining compatibility with nanometer technology processes
Solution Approach 2:
The patent employs composite gate structures combining metal materials with existing semiconductor materials, creating a hybrid system that leverages the low resistance properties of metals while maintaining the functional requirements of semiconductor devices
2Manufacturing precision
If multiple lithography operations are performed to achieve precise patterning, then manufacturing precision is improved, but the number of lithography operations increases
Solution Approach 1:
The patent merges multiple lithography operations into a single operation by using self-aligned material deposition and patterning techniques, where previously separate steps are combined into one integrated process flow
Solution Approach 2:
The patent performs preliminary material deposition and patterning actions before final gate formation, creating pre-patterned structures that guide subsequent processing steps and eliminate the need for additional lithography operations
3Ease of manufacture
If interlayer dielectric layers are formed without considering height differences, then manufacturing simplicity is maintained, but chemical mechanical polishing performance deteriorates
Solution Approach 1:
The patent performs preliminary etching to create steps in the substrate before forming interlayer dielectric layers, proactively addressing potential CMP issues before they arise during subsequent processing
Solution Approach 2:
The patent introduces localized height variations (steps) in specific areas of the substrate to create favorable conditions for CMP processing in those regions, while maintaining overall manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact and gate resistances and minimizes the increase in lithography operations by forming metal erase and select gates, enhancing the manufacturing efficiency and performance of semiconductor devices.
Implementation Method 1
a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas
Implementation Method 2
replacement of polysilicon layers with metal materials for the erase and select gates, reducing resistance
Data Source
AI summary
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.