Metal Gate Semiconductor Device with High-k Dielectric and Passivation
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Solution Overview
Problem
As transistors shrink, the resistance of polysilicon gate electrodes increases, preventing high-speed operation, and the integration of high dielectric constant gate oxide and metal gates poses compatibility issues with high temperature processes and work function control.
Innovation Solution
A semiconductor device with a high dielectric constant (high-k) layer and a diffusion layer of metal oxide, where a passivation layer prevents oxidation and a metal gate is formed on the passivation layer, with metal atoms diffused into the high-k layer to enhance dielectric constant and work function adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon gate electrodes are used, then the device structure is simple and manufacturing is easy, but resistance increases as transistors shrink, preventing high-speed operation
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or titanium nitride), fundamentally altering the electrical resistance characteristic to enable low-resistance, high-speed operation in scaled transistors
Solution Approach 2:
The patent employs a composite gate structure combining metal gate electrode with high-k dielectric material (such as hafnium oxide, zirconium oxide, or titanium oxide), creating a metal-oxide-semiconductor (MOS) structure that simultaneously achieves low resistance and high dielectric constant for improved transistor performance
2Reliability
If high dielectric constant gate oxide and metal gate are integrated, then transistor performance improves, but compatibility with high temperature processes deteriorates
Solution Approach 1:
The patent performs preliminary formation of the metal gate electrode and high-k dielectric layer before subsequent high-temperature processing steps, and introduces a protective passivation layer (such as aluminum oxide or silicon nitride) to prevent degradation during high-temperature annealing or source/drain formation processes
Solution Approach 2:
The patent introduces a passivation layer as an intermediary protective barrier between the metal gate/high-k dielectric structure and the high-temperature processing environment, preventing unwanted oxidation or diffusion while allowing the device to withstand necessary thermal processing
3Reliability
If high dielectric constant gate oxide and metal gate are integrated, then transistor performance improves, but work function control becomes difficult
Solution Approach 1:
The patent applies different metal materials or compositions to different regions of the gate electrode (such as using tungsten for NFET and cobalt or titanium nitride for PFET), or creates graded compositional profiles within the metal gate layer to precisely control the work function for specific transistor types and applications
Solution Approach 2:
The patent controls the work function by adjusting material composition parameters (such as the ratio of metals in an alloy, or the stoichiometry of metal nitrides/oxides), film thickness, and microstructure of the metal gate electrode to achieve desired electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces gate leakage current and improves transistor performance by adjusting the work function and increasing the dielectric constant of the high-k layer, enabling better integration of high-k gate oxide and metal gates.
Implementation Method 1
A passivation layer is disposed on the diffusion layer
Implementation Method 2
Metal atoms of the metal oxide are diffused into the high-k layer of the first trench and the substrate under the first trench by thermally heating the substrate
Implementation Method 3
by thermally heating the substrate
Data Source
AI summary
A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.