Metal Gate Semiconductor Manufacturing Process Simplification
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Solution Overview
Problem
Conventional dual metal gate processes for semiconductor devices face complexities in compatibility and precise material control, leading to issues like non-linear flat band voltage roll-off and leakage current due to re-crystallization of high-K gate dielectric layers, necessitating simplification of manufacturing processes.
Innovation Solution
A method involving the use of sacrifice gates for forming trenches and filling them with metal layers, where only one CMP process is required, allowing for improved yield and prevention of bad metal layer filling, and incorporating work function metal layers to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dual metal gate processes are used, then metal gates can be formed for NMOS and PMOS devices, but the process becomes complicated with non-linear flat band voltage roll-off and leakage current issues
Solution Approach 1:
The patent divides the gate formation process into separate sequential steps for NMOS and PMOS devices. First, a first metal layer is formed for NMOS devices, then a second metal layer is formed for PMOS devices. This segmentation allows independent optimization of each metal layer's properties and simplifies process control compared to conventional dual metal gate approaches where both metals must be formed simultaneously.
Solution Approach 2:
The patent performs the metal gate formation before the anneal process and silicide formation. By establishing the metal gates early in the process sequence, subsequent high-temperature processes can be optimized without compromising gate integrity, eliminating the need for strict heat budget constraints that cause Vfb roll-off in conventional approaches.
2Reliability
If gate last process is used to improve Vfb roll-off issue, then leakage current due to re-crystallization can be avoided, but the manufacturing process becomes more complicated
Solution Approach 1:
The patent inverts the conventional gate last process sequence by forming metal gates before the anneal and silicide processes rather than after. This inversion allows high-temperature processes to occur without causing gate re-crystallization or Vfb roll-off, while actually simplifying the overall process by eliminating the need for sacrifice gates and gate trench formation.
3Manufacturing precision
If conventional CMP process is used for metal layer formation, then planarization can be achieved, but yield is reduced due to bad metal layer filling issues
Solution Approach 1:
The patent changes the material parameters of the metal layers used as sacrifices. By selecting metals with specific properties that fill trenches reliably without requiring aggressive CMP, the process achieves both planarization and high yield. The first and second metal layers are designed with parameters that ensure complete trench filling while maintaining compatibility with subsequent processing steps.
Data Source
AI summary
The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.