Metal Gate Electrode Profiles for Lower Sheet Resistance
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Solution Overview
Problem
Polysilicon gate electrodes in integrated circuits have higher resistivity than metal materials, leading to slower operation speeds, necessitating the development of metal gates with reduced sheet resistance for improved performance and reliability.
Innovation Solution
A metal gate structure is fabricated with a substrate divided into N-type and P-type transistor regions, featuring trenches with specific profiles for gate electrodes, work function layers, and dielectric layers, and a method involving multiple removing processes to shape the metal layer into bullet-shaped and mushroom-shaped profiles, reducing sheet resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon gate electrodes are used, then thermal resistive properties are maintained, but resistivity is higher leading to slower operation speeds
Solution Approach 1:
The patent employs a composite gate electrode structure consisting of multiple metal layers (e.g., tungsten, copper, aluminum) combined with work function adjustment layers. This composite approach achieves both low resistivity for high-speed operation and controlled thermal properties, resolving the contradiction between speed and thermal performance.
Solution Approach 2:
The patent changes the material parameters of the gate electrode by transitioning from polysilicon to metal-based materials with adjustable composition and structure. By controlling layer thicknesses, material compositions, and annealing conditions, the patent optimizes both electrical resistivity and thermal characteristics to achieve superior operation speed while maintaining reliability.
2Productivity
If metal gates are used to replace polysilicon, then operation speed improves, but sheet resistance needs further reduction for superior performance
Solution Approach 1:
The gate electrode is segmented into multiple functional layers: bottom metal layers for low resistivity and high conductivity, intermediate layers for mechanical support, and top work function layers for threshold voltage control. This segmentation allows each layer to be optimized independently, achieving ultra-low sheet resistance while maintaining overall gate performance.
Solution Approach 2:
The metal gate structure serves multiple functions simultaneously: the metal layers provide low resistivity for high-speed operation, the work function layers enable threshold voltage adjustment, and the layered structure provides mechanical stability. This multi-functionality achieves superior performance while controlling sheet resistance through integrated design.
3Reliability
If complex trench profiles are formed, then gate electrode performance is optimized, but fabrication process complexity increases
Solution Approach 1:
The patent forms the complex trench profiles and multi-layer structures through preliminary fabrication steps including selective epitaxial growth, controlled deposition, and patterned etching. By establishing the correct geometry and material distribution early in the process, subsequent steps are simplified, and gate electrode performance is optimized without requiring excessively complex later processing.
Solution Approach 2:
The patent replaces purely mechanical/morphological approaches with chemistry-based processes such as selective chemical vapor deposition, atomic layer deposition, and wet/dry etching. These processes enable precise control of layer thicknesses, compositions, and trench profiles through chemical reactions rather than mechanical means, achieving high performance while managing fabrication complexity.
Data Source
AI summary
A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.