Metal Gate Separation Structure to Prevent Interconnect Short Circuits
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Solution Overview
Problem
The existing semiconductor technologies face challenges in preventing short circuits between the interconnection metal layer and the metal gate, which affects the quality and performance of semiconductor devices.
Innovation Solution
A semiconductor device with a gate structure featuring a separation section made of SiNx, SiO2, or SiON, where the top surface of the separation section is higher than the gate structure, and a method involving a sacrificial layer and atomic layer deposition to form the separation section, increasing the distance between the metal layer and the gate structure and reducing the likelihood of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interconnection metal layer is formed on the metal gate to form electrical connection, then electrical connection with the outside world is achieved, but short circuit容易发生 between the interconnection metal layer and the metal gate
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the metal gate and the interconnection metal layer. This dielectric layer acts as a physical barrier that prevents direct contact between the conductive metal gate and the interconnection metal layer, thereby eliminating the short circuit risk while still allowing electrical connection to be achieved through proper via and contact hole formation in the dielectric layer.
Solution Approach 2:
The patent segments the gate structure into multiple portions (first portion, second portion, third portion) with different lengths in different regions. This segmentation allows for optimized electrical connection in each region while maintaining overall device performance and reducing short circuit risk through differentiated design.
2Productivity
If the gate structure length is reduced to improve production efficiency, then manufacturing cost is reduced, but device performance may be affected
Solution Approach 1:
The patent applies local quality by making different portions of the gate structure have different lengths tailored to the specific requirements of each region. The first portion has a first length, the second portion has a second length, and the third portion has a third length, allowing each region to be optimized for its specific function while maintaining overall device performance and production efficiency.
Solution Approach 2:
The patent employs asymmetric gate structure design where the lengths of different gate portions are intentionally made unequal. This asymmetric design allows for optimized electrical connection and device performance in different regions without requiring uniform length reduction across the entire gate structure, thereby maintaining performance while improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the possibility of short circuits and improves the stability and performance of semiconductor devices by creating a sufficient height difference between the metal layer and the gate structure.
Implementation Method 1
A top surface of the separation section is higher than a top surface of the gate structure
Data Source
AI summary
A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure.