Semiconductor Metal Gate Etching With Sidewall Passivation

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Solution Overview

Problem

Existing methods of etching metal and dielectric layers in semiconductor fabrication face challenges in achieving adequate selectivity and profile control, particularly as device features shrink, complicating the integration of metal gate cutting processes.

Innovation Solution

A two-step etching process using a first etchant and a second etchant combined with a passivant in reactive plasma to etch metal and dielectric layers, forming a passivation layer on metal sidewalls to enhance selectivity and control the profile, allowing for improved etching of high aspect-ratio features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single etching process is used to etch both metal and dielectric layers, then processing steps are reduced, but etching selectivity and profile control deteriorate

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidetching selectivity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is divided into two distinct steps: a first etching process using a fluorine-containing gas to etch the metal layer, and a second etching process using a different etchant to etch the dielectric layer. This segmentation allows each etching process to be optimized for its specific target material, achieving high etching selectivity while maintaining efficient processing through sequential execution.

Inventive Principle:
Principle #1Segmentation

2Productivity

If device features are reduced in critical dimension, then device density increases, but etching profile control becomes more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidprofile control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies different etching conditions and chemistries to different regions and depths of the structure. The first etching process uses fluorine-containing gas optimized for metal etching with specific profile characteristics, while the second etching process uses a different etchant optimized for dielectric etching. This local optimization of etching quality at each stage enables precise profile control even as critical dimensions decrease.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If existing etching methods are used for metal and dielectric layers, then processing is simpler, but etching selectivity and profile control are inadequate

Engineering Contradiction:
Improveprocessing simplicityVSAvoidetching selectivity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The etching process is divided into two distinct steps: a first etching process using a fluorine-containing gas to etch the metal layer, and a second etching process using a different etchant to etch the dielectric layer. This segmentation allows each etching process to be optimized for its specific target material, achieving high etching selectivity while maintaining efficient processing through sequential execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes key etching parameters between the two processes, including etchant chemistry (fluorine-containing gas vs. other etchants), plasma power, pressure, and gas flow rates. These parameter changes enable optimization of each etching step for its specific target material, achieving superior selectivity and profile control compared to single-process methods.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances etching selectivity and profile control, reducing metal loss during dielectric etching, widening the processing window, and increasing throughput by using a combined etchant and passivant in a reactive plasma.

Implementation Method 1

performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS12610763B2Semiconductor devices and methods of manufacturing the same
Publication Date: 2026.04.21 TOKYO ELECTRON LTD
  • US12610763B2 patent drawing
  • US12610763B2 patent drawing
  • US12610763B2 patent drawing

AI summary

A method includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. The method includes forming a metal layer over the dielectric layer. The method includes forming a patterned mask over the metal layer. The method includes performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer. The method further includes performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns.