Metal Gate Spacer Formation for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor transistors scale down, issues such as damaged spacer structures and increased parasitic capacitance due to high-k dielectric materials lead to compromised device performance, necessitating an alternative approach to reduce parasitic capacitance and enhance speed.
Innovation Solution
The implementation of in-situ selective heating assisted plasma etching operations increases etch selectivity between target and adjacent dielectric materials, allowing for the precise removal of sacrificial spacers and gate dielectrics without damaging nearby structures, thereby reducing parasitic capacitance and improving device speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-k dielectric materials are used to reduce parasitic capacitance, then device speed is improved, but spacer structures are damaged and manufacturing complexity increases
Solution Approach 1:
The patent segments the dielectric materials into different types (first dielectric material with higher etch selectivity and second dielectric material with lower etch selectivity), allowing selective removal of sacrificial spacers without damaging other structures. This segmentation enables precise control over which materials are etched first, resolving the contradiction between using high-k dielectrics and maintaining spacer integrity.
Solution Approach 2:
The patent changes the etch selectivity parameter by introducing a first dielectric material with higher etch selectivity compared to the second dielectric material. This parameter change allows the sacrificial spacers to be removed selectively without damaging the high-k dielectric structures, thereby improving device speed while controlling processing complexity.
2Ease of manufacture
If conventional etching is used to remove sacrificial spacers, then manufacturing simplicity is maintained, but adjacent dielectric materials are damaged
Solution Approach 1:
The patent applies local quality by making different regions of the dielectric structure have different etch selectivity properties. The first dielectric material (sacrificial spacer) has higher etch selectivity than the second dielectric material (adjacent structures), enabling selective removal of the sacrificial spacers without damaging adjacent materials. This resolves the contradiction between manufacturing simplicity and preventing damage.
Solution Approach 2:
The patent changes the etch selectivity parameter between different dielectric materials, allowing the first dielectric material to be etched preferentially. This parameter change enables simple manufacturing processes to selectively remove sacrificial spacers without causing harmful effects to adjacent structures.
3Manufacturing precision
If multiple separate processes are used for selective heating and plasma etching, then process precision is improved, but productivity decreases
Solution Approach 1:
The patent merges the selective heating process and plasma etching process into a single integrated process. The first dielectric material is selectively heated and etched in the same process step, achieving both the precision of selective removal and the productivity of combined operations. This resolves the contradiction between manufacturing precision and productivity.
Solution Approach 2:
The patent implements continuous useful action by combining heating and etching in one continuous process step. The selective heating of the first dielectric material is immediately followed by its etching without interrupting the process flow, maintaining both precision and productivity. This eliminates the need for separate process steps while preserving etch selectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces parasitic capacitance and enhances transistor speed while lowering production costs and increasing efficiency by performing selective heating in the same chamber as plasma etching.
Implementation Method 1
A treatment is preformed to selectively heat a bonding between a first atom and a second atom of the sacrificial spacer
Implementation Method 2
The sacrificial spacer is selectively etched to reduce a thickness of the sacrificial spacer
Data Source
AI summary
A method for forming a semiconductor structure is provided. A structure including a sacrificial spacer interposed between a metal gate structure and a dielectric structure is received. A temperature of the sacrificial spacer is increased. At least a portion of the sacrificial spacer is removed to form a recess between the metal gate structure and the dielectric structure. A spacer is formed in the recess along a sidewall of the metal gate structure. A semiconductor structure is also provided.