Metal Gate Stack Spacer Doping for Lower RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at smaller sizes due to increased complexity and difficulty in fabrication processes as feature sizes decrease, leading to issues with forming reliable semiconductor devices at smaller sizes.
Innovation Solution
A method involving the formation of a semiconductor device structure that includes forming a dummy gate stack, spacer elements, and source/drain structures, followed by partial removal of the dummy gate electrode and spacer elements to create recesses, doping the spacer elements to reduce the dielectric constant, and replacing the dummy gate with a metal gate stack, which improves the reliability and performance of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming dummy gate stacks, forming spacer elements, selectively removing portions to create recesses, doping spacer elements, and forming metal gate stacks. This segmentation allows each stage to be optimized independently, managing the overall process complexity while achieving smaller feature sizes
Solution Approach 2:
Dummy gate stacks are formed preliminarily before the actual metal gate stacks. These dummy structures serve as placeholders that guide subsequent processing steps, including spacer formation and selective removal, enabling precise patterning at smaller dimensions while simplifying the overall fabrication flow
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The dielectric constant of spacer elements is modified through doping with materials such as silicon nitride or silicon oxynitride. This parameter change reduces RC delay and improves signal integrity, thereby enhancing device reliability at smaller feature sizes while maintaining high functional density
Solution Approach 2:
Spacer elements serve as intermediary structures that define the boundaries for metal gate stack formation. These spacers provide mechanical support and electrical isolation, ensuring reliable device operation during the transition from dummy gates to functional metal gates at scaled dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of semiconductor devices by reducing RC delay and improving carrier mobility, while facilitating the transition from smaller feature sizes by maintaining the structural integrity and functionality of the semiconductor device.
Implementation Method 1
doping the spacer elements to reduce the dielectric constant
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant contains halide. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.