Metal Gate Spacer Height Control for FinFET Air Gap Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of air gaps in FinFET structures during the fabrication of semiconductor devices can lead to structural complications and shorting issues due to differences in height between gate structures in active and isolation regions, affecting the capacitance and integrity of the gate structures.
Innovation Solution
A method is developed to selectively remove top portions of the gate spacer layer in the isolation region while maintaining the gate spacer layer in the active device region, ensuring the structural integrity of high-k metal gate structures by controlling the etching process to adjust the height of the remaining gate spacer portions, thereby preventing collapse and shorting issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gaps are formed in FinFET structures during fabrication, then capacitance is reduced and device performance is improved, but structural complications and shorting issues occur due to height differences between gate structures in active and isolation regions
Solution Approach 1:
The patent applies local quality by forming air gaps selectively only in the active device region while maintaining solid dielectric material in the isolation region. This is achieved through a multi-step process where the gate spacer is differentially etched: first, the gate spacer is removed from the isolation region while retained in the active region; second, air gaps are formed only in the active region between the gate structure and interlayer dielectric. This local differentiation resolves the contradiction by providing the capacitance reduction benefits of air gaps in active devices while avoiding structural complications in isolation regions where they are unnecessary.
2Reliability
If the gate spacer layer is removed to form air gaps, then capacitance is reduced for improved device performance, but the structural integrity of high-k metal gate structures is compromised leading to collapse and shorting
Solution Approach 1:
The patent applies preliminary action by performing a selective etching step before air gap formation that removes the gate spacer from the isolation region while retaining it in the active region. This preliminary differentiation creates a stable structural foundation: the gate spacer remains in the active region to provide mechanical support during subsequent air gap formation, preventing collapse, while its removal in the isolation region enables proper isolation structure formation. This sequential, region-specific approach ensures structural integrity is maintained where needed while enabling capacitance optimization where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of FinFET structures by maintaining the air gap in the active device region while ensuring the structural integrity of the high-k metal gate structures in the isolation region, reducing capacitance and preventing shorting issues.
Implementation Method 1
controlling the etching process to adjust the height of the remaining gate spacer portions
Data Source
AI summary
A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.