Metal Gate Thermal Stability via Impurity Implantation
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to thermal and morphological instability of metal gate electrodes, resulting in poor and unpredictable process control, variations in device characteristics such as gate resistance and threshold voltage, due to the thermal and morphological instability of fill metal layers.
Innovation Solution
A method involving the formation of a semiconductor device with a high-k metal gate, where a dummy gate is removed to create a trench, and a work function metal layer and fill metal layer are deposited, followed by chemical mechanical polishing (CMP) and impurity atom implantation, such as Si, C, or Ge, to improve the thermal and morphological stability of the metal gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate electrode is used to improve device performance, then device performance is improved, but thermal and morphological stability deteriorates during subsequent processing
Solution Approach 1:
The patent changes the chemical composition parameters of the fill metal layer by incorporating impurity atoms (Si, C, or Ge) to transform the metal from an unstable pure form to a stable alloy form. This parameter change resolves the contradiction by maintaining device performance while achieving thermal and morphological stability during subsequent processing.
Solution Approach 2:
The patent creates a composite metal layer structure by combining the fill metal with impurity atoms (Si, C, or Ge). This composite approach resolves the contradiction by integrating multiple elements that provide both the electrical performance needed for device operation and the thermal/morphological stability required for subsequent processing.
2Ease of manufacture
If fill metal layer is deposited to form metal gate, then manufacturing process is simplified, but process control precision deteriorates due to instability
Solution Approach 1:
The patent modifies the compositional parameters of the fill metal layer by adding impurity atoms, which transforms the material properties to achieve stability. This resolves the contradiction by maintaining ease of deposition while achieving the precision and control needed for predictable device characteristics.
3Productivity
If feature size is scaled down to increase production efficiency, then productivity is improved, but thermal and morphological stability of metal gate deteriorates
Solution Approach 1:
The patent changes the compositional parameters of the metal gate by incorporating impurity atoms at controlled concentrations. This resolves the contradiction by enabling continued scaling for productivity while the modified composition maintains thermal and morphological stability even at reduced feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The incorporation of impurity atoms into the fill metal layer enhances the thermal and morphological stability, reducing variations in device characteristics and improving process control, leading to more reliable semiconductor device performance.
Implementation Method 1
implanting one of Si, C, and Ge into a remaining portion of the fill metal layer
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.