Tri-layer Metal Gate Stack for CMOS Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in implementing metal gate structures for both NMOS and PMOS transistors on a single substrate, particularly in CMOS fabrication, due to the complexity of processing and manufacturing as technology nodes shrink.
Innovation Solution
A method for fabricating semiconductor devices with differently configured metal gate structures involves forming a tri-layer element with a metal gate layer interposed between capping layers, where the capping layers are patterned and used to create distinct gate stacks for NMOS and PMOS devices, utilizing high-k dielectric layers and specific materials like hafnium oxide and lanthanum oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate structure is implemented for both NMOS and PMOS transistors on a single substrate, then device performance is improved, but processing and manufacturing complexity increases
Solution Approach 1:
The gate stack is segmented into distinct layers including a first capping layer, metal gate layer, and second capping layer. The second capping layer is selectively removed in NMOS regions while retained in PMOS regions, enabling different gate configurations for different device types on the same substrate without requiring completely separate processing lines.
Solution Approach 2:
The patent applies local quality by having different gate structures in different regions of the substrate. NMOS devices have a gate structure with the second capping layer removed exposing the metal gate layer, while PMOS devices retain the second capping layer. This localized differentiation allows optimized performance for each transistor type while using a unified base process.
2Adaptability or versatility
If differently configured gate structures are formed for NMOS and PMOS devices, then tailored work functions are achieved, but the number of fabrication steps increases
Solution Approach 1:
The tri-layer gate stack structure with first capping layer, metal gate layer, and second capping layer is formed preliminarily across the entire substrate before any selective removal. This preliminary formation of the complete structure allows subsequent selective etching to create different gate configurations without requiring separate formation processes for NMOS and PMOS devices.
Solution Approach 2:
The second capping layer is selectively taken out (removed) from NMOS regions through selective etching while being retained in PMOS regions. This extraction approach allows the same base structure to be differentiated into two functional types by removing material only where needed, rather than forming two completely different structures from scratch.
3Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the form of selective etching conditions to achieve precise differentiation at small feature sizes. By controlling etch selectivity between the first and second capping layers, the process can reliably distinguish and treat different regions with sub-micron precision, maintaining manufacturing precision even as feature sizes decrease for higher functional density.
Data Source
AI summary
A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.