Metal Gate Stack Etching Back at Controlled Temperature
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues in processing and manufacturing.
Innovation Solution
The process involves forming FinFET structures with fins patterned using photolithography and self-aligned processes, including double-patterning or multi-patterning techniques, and forming metal gate stacks with specific etching and deposition methods to create a gate dielectric layer and work function layer, followed by an etching back process at a controlled temperature to ensure high selectivity and protect spacer elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate dielectric layer, work function layer, and metal gate electrode layer. This segmentation allows each layer to be optimized independently for its specific function, enabling reliable device formation at smaller sizes while managing fabrication complexity through modular processing steps.
Solution Approach 2:
The patent employs parameter changes in the etching process by controlling temperature (maintaining metal gate stack at 20-55°C) and using selective etching chemistry to achieve high etching selectivity between different materials. This allows precise formation of metal gate stacks at reduced feature sizes with controlled dimensions and improved fabrication reliability.
2Manufacturing precision
If etching selectivity between work function layer and gate dielectric layer is enhanced, then metal gate stack integrity is improved, but process complexity increases
Solution Approach 1:
The etching process utilizes parameter changes by controlling temperature (20-55°C) and selecting specific etching chemistry to achieve high etching selectivity between the work function layer and gate dielectric layer. This allows precise differentiation between materials with controlled processing parameters, achieving manufacturing precision without requiring overly complex process sequences.
Solution Approach 2:
The work function layer serves as an intermediary layer between the gate dielectric and metal gate electrode. This intermediary enables selective etching processes to differentiate between materials, providing both structural integrity and process control while simplifying the overall fabrication approach compared to direct metal gate formation.
3Reliability
If spacer elements are protected during etching, then device reliability is improved, but additional process steps are required
Solution Approach 1:
The metal gate stack is formed preliminarily before the spacer elements are fully removed or modified. This preliminary action allows the metal gate stack to serve as a protective template during subsequent etching processes, ensuring spacer element integrity is maintained while enabling reliable device formation without requiring additional protective layer deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of semiconductor devices by maintaining the integrity of spacer elements and enhancing the etching selectivity between the work function layer and the gate dielectric layer, thereby ensuring the semiconductor device structure's performance and reliability.
Implementation Method 1
removing an upper portion of the metal gate stack using an etching process
Implementation Method 2
forming metal gate stacks with specific etching and deposition methods to create a gate dielectric layer and work function layer
Data Source
AI summary
A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.